請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99443完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平 | zh_TW |
| dc.contributor.advisor | Chung-Ping Chen | en |
| dc.contributor.author | 廖哲強 | zh_TW |
| dc.contributor.author | CHE-CHIANG LIAO | en |
| dc.date.accessioned | 2025-09-10T16:18:15Z | - |
| dc.date.available | 2025-09-11 | - |
| dc.date.copyright | 2025-09-10 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-01 | - |
| dc.identifier.citation | [1] Y. C. Hu, Y. M. Liang, H. P. Hu, C. Y. Tan, C. T. Shen, C. H. Lee, and S. Y. Hou, "CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package," in Proc. IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 1022–1026.
[2] S. P. Jeng and M. Liu, "Heterogeneous and Chiplet Integration Using Organic Interposer (CoWoS-R)," in IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 3.2.1–3.2.4. [3] P. Y. Lin, M. Yew, S. Yeh, S. M. Chen, C. H. Lin, C. Chen, C. Hsieh, Y. Lu, P. Chuang, H. K. Cheng, and S. Jeng, "Reliability Performance of Advanced Organic Interposer (CoWoS-R) Packages," in Proc. IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, pp. 723–728. [4] M. S. Lin, T.-C. Huang, C.-C. Tsai, K. Tam, K. Hsieh, C.-F. Chen, W.-H. Huang, C.-W. Hu, Y.-C. Chen, S. Goel, C.-M. Fu, S. Rusu, C.-C. Li, S.-Y. Yang, M. Wong, S.-C. Yang, and F. Lee, "A 7-nm 4-GHz Arm-Core-Based CoWoS Chiplet Design for High-Performance Computing," IEEE J. Solid-State Circuits, vol. 55, no. 4, pp. 956–966, Apr. 2020. [5] S. K. Goel, T. Chien, T. Y. Lin, Y.-C. Lu, Y.-H. Chien, and D. C. H. Yu, "Test and Debug Strategy for TSMC CoWoS Stacking Process Based Heterogeneous 3-D IC," in Proc. IEEE Int. Test Conf. (ITC), 2013, pp. 1–10. [6] L. Lin, T. Chien, W. Wu, Y.-C. Chen, and S. K. Goel, "Reliability Characterization of Chip-on-Wafer-on-Substrate 3-D IC Integration Technology," in Proc. IEEE 63rd Electronic Components and Technology Conference (ECTC), 2013, pp. 366–371. [7] C. F. Tseng, C. T. Wang, T. Ko, and S. Y. Hou, "InFO (wafer level integrated fan-out) technology," in Proc. IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, pp. 1–6. [8] C. T. Wang and D. Yu, "Signal and power integrity analysis on integrated fan-out PoP (InFO_PoP) technology for next generation mobile applications," in Proc. IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, pp. 380–385. [9] H. P. Pu, C. T. Wang, J. C. Chang, S. R. Chun, C. Y. Chen, and T. Ko, "A novel submicron polymer redistribution layer technology for advanced InFO packaging," in Proc. IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, pp. 45–51. [10] T. Ko, C. F. Tseng, S. R. Chun, C. T. Wang, and C. W. Hsu, "Applications and reliability study of InFO_UHD (ultra-high-density) technology," in Proc. IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, pp. 1120–1125. [11] S. R. Chun, T. Ko, Y. P. Chiang, C. W. Hsu, and C. T. Wang, "InFO_SoW (system-on-wafer) for high performance computing," in Proc. IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, pp. 1–6. [12] Y. P. Chiang, C. H. Hsu, C. W. Hsu, S. R. Chun, and C. T. Wang, "InFO_oS (integrated fan-out on substrate) technology for advanced chiplet integration," in Proc. IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, pp. 130–135. [13] C. T. Wang, C. W. Hsu, and D. Yu, "InFO_AiP technology for high performance and compact 5G millimeter wave system integration," in Proc. IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, pp. 202–207. [14] C. W. Hsu, T. Ko, S. R. Chun, and C. T. Wang, "High performance chip-partitioned millimeter wave passive devices on smooth and fine pitch InFO RDL," in Proc. IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, pp. 254–259. [15] C. T. Wang and D. Yu, "Power-performance advantages of InFO technology for advanced system integration," in Proc. IEEE Int. 3DIC Conf., 2019, pp. 1–4. [16] C. H. Hsu, Y. P. Chiang, C. T. Wang, and S. R. Chun, "Thermal characteristics of integrated fan-out on substrate (InFO_oS) packaging technology," in Proc. IEEE Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2020, pp. 212–218. [17] C. C. Hu, M. F. Chen, W. C. Chiou, and D. C. H. Yu, "3D multi-chip integration with system on integrated chips (SoIC)," in Symp. VLSI Technology, 2019, pp. T20–T21. [18] M. F. Chen, F. C. Chen, W. C. Chiou, and D. C. H. Yu, "System on integrated chips (SoIC) for 3-D heterogeneous integration," in Proc. IEEE Electronic Components and Technology Conference (ECTC), 2019, pp. 594–599. [19] C. H. Tsai, T. Ku, M. F. Chen, W. C. Chiou, C. T. Wang, and D. Yu, "Low-temperature SoIC bonding and stacking technology for 12/16-Hi high-bandwidth memory," in Symp. VLSI Technology, 2020, pp. 1–2. [20] M. F. Chen, C. S. Lin, E. B. Liao, W. C. Chiou, C. C. Kuo, C. C. Hu, C. H. Tsai, C. T. Wang, and D. Yu, "SoIC for low-temperature, multi-layer 3-D memory integration," in Proc. IEEE Electronic Components and Technology Conference (ECTC), 2020, pp. 855–860. [21] S. W. Liang, G. C. Y. Wu, K. C. Yee, C. T. Wang, J. J. Cui, and D. C. H. Yu, "High-performance and energy-efficient computing with advanced SoIC scaling," in Proc. IEEE Electronic Components and Technology Conference (ECTC), 2022, pp. 1090–1094. [22] D. C. H. Yu, C. T. Wang, C. C. Lin, C. H. Lu, G. Wu, C. Y. Huang, W. T. Chen, T. Ku, K. C. Yee, and C. H. Tsai, "SoIC_H technology for heterogeneous system integration," IEEE Trans. Electron Devices, vol. 69, no. 12, pp. 7167–7172, 2022. [23] Y. H. Chen, C. A. Yang, C. C. Kuo, M. F. Chen, C. H. Tung, W. C. Chiou, and D. Yu, "Ultra-high-density SoIC with sub-micron bond pitch," in Proc. IEEE Electronic Components and Technology Conference (ECTC), 2020, pp. 576–581. [24] H. J. Chia, S. P. Tai, J. J. Cui, C. T. Wang, C. H. Tung, K. C. Yee, and D. C. H. Yu, "Ultra-high-density low-temperature SoIC with sub-0.5 µm bond pitch," in Proc. IEEE Electronic Components and Technology Conference (ECTC), 2023, pp. 1–4. [25] M. N. Ozisik, "Finite Difference Methods in Heat Transfer." Boca Raton, FL, USA: CRC Press, 1994. [26] T. Y. Wang and C. C. P. Chen, "3-D thermal-ADI: A linear-time chip-level transient thermal simulator," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 12, pp. 1434–1445, Dec. 2002. [27] W. Huang et al., "HotSpot: A compact thermal modeling methodology for early-stage VLSI design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 5, pp. 501–513, May 2006. [28] J. Li, M. Tang, and J. Mao, "An efficient ADI method for transient thermal simulation of liquid-cooled 3-D ICs," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 12, no. 9, pp. 1484–1491, Sep. 2022. [29] R. W. Lewis, P. Nithiarasu, and K. N. Seetharamu, "Fundamentals of the Finite Element Method for Heat and Fluid Flow." Chichester, U.K.: Wiley, 2004. [30] P. Li, L. T. Pileggi, M. Asheghi, and R. Chandra, "Efficient full-chip thermal modeling and analysis," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), 2004, pp. 319–326. [31] D. Oh, C. C. P. Chen, and Y. H. Hu, "Efficient thermal simulation for 3-D IC with thermal through-silicon vias," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 31, no. 11, pp. 1767–1771, Nov. 2012. [32] B. Li, M. Tang, Y. Zhi, and H. Yu, "Thermal simulation of 3-D stacked integrated circuits with layered finite element method," in Proc. PIERS-Fall, 2019, pp. 1883–1886. [33] B. Li, M. Tang, P. Li, and J. Mao, "Efficient thermal analysis of integrated circuits and packages with microchannel cooling using Laguerre-based layered FEM," IEEE J. Microwaves, Microw. Compon. Lett., vol. 8, pp. 195–204, 2023. [34] L. Codecasa et al., "Fast novel thermal analysis simulation tool for integrated circuits (FANTASTIC)," 20th International Workshop on Thermal Investigations of ICs and Systems, Greenwich, UK, 2014, pp. 1-6. [35] K. W. Yan, P. Y. Lin, and S. L. Kuo, "Thermal challenges for HPC 3DFabric packages and systems," in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), 2022, pp. 4C.1–4C.1–6. [36] K. Yan, P. Y. Lin, and S. L. Kuo, "Thermal challenges for HPC 3DIC packages and systems," in Proc. IEEE Electron Devices Technol. Manuf. Conf. (EDTM), 2022, pp. 151–153. [37] S. P. Gurrum, S. K. Suman, Y. K. Joshi, and A. G. Fedorov, "Thermal issues in next-generation integrated circuits," IEEE Trans. Device Mater. Reliab., vol. 4, no. 4, pp. 709–714, Dec. 2004. [38] F. Tavakkoli, S. Ebrahimi, S. Wang, and K. Vafai, "Analysis of critical thermal issues in 3-D integrated circuits," Int. J. Heat Mass Transfer, vol. 97, pp. 337–352, Jan. 2016. [39] Y. L. Shen, "Analysis of Joule heating in multilevel interconnects," J. Vac. Sci. Technol. B, vol. 17, no. 5, pp. 2115–2121, Sep./Oct. 1999. [40] B. Bai, S. Chen, W. Wang, H. Hao, and L. Li, "Thermal management of integrated circuits in burn-in environment," in Proc. Int. Conf. Rel., Maintainability and Safety, 2011, pp. 1092–1095. [41] S. Shi, X. Zhang, and R. Luo, "Thermal-aware floorplanning for 3-D ICs using carbon nanotube," in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), 2010, pp. 1155–1158. [42] A. L. Moore and L. Shi, "Emerging challenges and materials for thermal management of electronics," Mater. Today, vol. 17, no. 4, pp. 163–174, Apr. 2014. [43] A. Quarteroni and A. Valli, "Domain Decomposition Methods for Partial Differential Equations." Oxford, U.K.: Oxford Univ. Press, 1999. [44] A. Toselli and O. B. Widlund, "Domain Decomposition Methods—Algorithms and Theory." Berlin, Germany: Springer, 2004. [45] W. Yu, T. Zhang, X. Yuan, and H. Qian, "Fast 3-D thermal simulation for integrated circuits with domain decomposition method," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 32, no. 12, pp. 2014–2018, Dec. 2013. [46] J. Xie and M. Swaminathan, "System-level thermal modeling using nonconformal domain decomposition and model-order reduction," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 4, no. 1, pp. 66–76, Jan. 2014. [47] N. Liu et al., "The domain decomposition method with adaptive time step for the transient thermal analysis of 3-D ICs," IEEE Access, vol. 11, pp. 48069–48079, 2023. [48] L. Tang and Y. K. Joshi, "A multigrid-based multiscale thermal analysis approach for combined mixed convection, conduction, and radiation," ASME J. Heat Transfer, vol. 127, no. 3, pp. 1–9, Mar. 2005. [49] Peng Li, L. T. Pileggi, M. Asheghi and R. Chandra, "Efficient full-chip thermal modeling and analysis," IEEE/ACM International Conference on Computer Aided Design, 2004. (ICCAD), San Jose, USA, pp. 319-326, 2004. [50] M. Pedram and S. Nazarian, "Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods," Proceedings of the IEEE, vol. 94, no. 8, pp. 1487-1501, 2006. [51] A. Jain, R. E. Jones, Ritwik Chatterjee, S. Pozder and Zhihong Huang, "Thermal modeling and design of 3D integrated circuits," 2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Orlando, USA, pp. 1139-1145, 2008. [52] Sungjun Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," International Electron Devices Meeting 2000. Technical Digest. (IEDM), San Francisco, USA, pp. 727-730, 2000. [53] Z. Cao, J. Li, J. Tao and Y. Chen, "3D Compact Thermal Model and its Application on Fast Chip Level Thermal Simulation," 2023 International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, pp. 246-249, 2023. [54] A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler and D. Atienza, "3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling," 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, pp. 463-470, 2010. [55] M. N. Ozisik, "Finite Difference Methods in Heat Transfer," New York:CRC, 1994. [56] Wei Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron and M. R. Stan, "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 5, pp. 501-513, 2006. [57] T. Y. Wang and Charlie C. P. Chen, "3-D Thermal-ADI: a linear-time chip level transient thermal simulator," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ICCAD), vol. 21, no. 12, pp. 1434-1445, 2002. [58] J. Li, M. Tang and J. Mao, "An Efficient ADI Method for Transient Thermal Simulation of Liquid-Cooled 3-D ICs," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 9, pp. 1484-1491, 2022. [59] R. W. Lewis, P. Nithiarasu, K. N. Seetharamu, "Fundamentals of the Finite Element Method for Heat and Fluid Flow," Wiley, 2004. [60] B. Li, M. Tang, Y. Zhi and H. Yu, "Thermal Simulation of 3-D Stacked Integrated Circuits with Layered Finite Element Method," 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall), Xiamen, China, pp. 1883-1886, 2019. [61] B. Li, M. Tang, P. Li and J. Mao, "Efficient Thermal Analysis of Integrated Circuits and Packages With Microchannel Cooling Using Laguerre-Based Layered Finite Element Method," IEEE Journal on Multiscale and Multiphysics Computational Techniques, vol. 8, pp. 195-204, 2023. [62] D. Oh, C. C. P. Chen and Y. H. Hu, "Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 11, pp. 1767-1771, 2012. [63] L. Codecasa, V. d'Alessandro, A. Magnani, N. Rinaldi and P. J. Zampardi, "Fast novel thermal analysis simulation tool for integrated circuits (FANTASTIC)," 20th International Workshop on Thermal Investigations of ICs and Systems, Greenwich, UK, 2014, pp. 1-6. [64] Ansys, "Ansys Collaborates with TSMC to Deliver Thermal Analysis Solution for 3D IC Designs," https://www.ansys.com/en-in/news-center/press-releases/10-27-21-ansys-collaborates-with-tsmc-to-deliver-thermal-analysis-solution-for-3d-ic-designs, 2021. [65] M. Roshandell, "Successful Thermal Management of 3D-ICs: Accurate, Fast, Efficient and Scalable with Celsius," https://community.cadence.com/cadence_blogs_8/b/pcb/posts/successful-thermal-management-of-3d_2d00_ics, 2022. [66] Z. Tokei, H. Oprins, M. Lofrano, and X. Chang, "Mitigating the thermal bottleneck in advanced interconnects," Chip Scale Review, vol. 27, pp. 43-48, 2023. [67] B. Allard, X. Jorda, P. Bidan, A. Rumeau, H. Morel, X. Perpina, M. Vellvehi and S. M'Rad, "Reduced-Order Thermal Behavioral Model Based on Diffusive Representation," in IEEE Transactions on Power Electronics, vol. 24, no. 12, pp. 2833-2846, 2009. [68] X. Dong, A. Griffo, D. Hewitt and J. Wang, "Reduced-Order Thermal Observer for Power Modules Temperature Estimation," in IEEE Transactions on Industrial Electronics, vol. 67, no. 12, pp. 10085-10094, 2020,. [69] A. Quarteroni, A. Valli, "Domain Decomposition Methods for Partial Differential Equations," Oxford University Press, 1999. [70] A. Toselli, Olof B. Widlund, "Domain Decomposition Methods - Algorithms and Theory," Springer, 2004. [71] W. Yu, T. Zhang, X. Yuan and H. Qian, "Fast 3-D Thermal Simulation for Integrated Circuits With Domain Decomposition Method," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 12, pp. 2014-2018, 2013. [72] N. Liu, C. Wang, C. Xi, Q. Wu, Q. Liu, M. Zhuang, L. Shi and Q. H. Liu, "The Domain Decomposition Method With Adaptive Time Step for the Transient Thermal Analysis of 3-D ICs," in IEEE Access, vol. 11, pp. 48069-48079, 2023. [73] X. Zhang and M. Tang, "Non-Conformal Domain Decomposition Method for Thermal Analysis of Integrated Packages," 2022 IEEE 10th Asia-Pacific Conference on Antennas and Propagation (APCAP), Xiamen, China, pp. 1-2, 2022. [74] J. Xie and M. Swaminathan, "System-Level Thermal Modeling Using Nonconformal Domain Decomposition and Model-Order Reduction," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, no. 1, pp. 66-76, 2014. [75] B. Barabadi, S. Kumar, V. Sukharev, Y. K. Joshi, "Multiscale Transient Thermal Analysis of Microelectronics." Journal of Electronic Packaging, vol. 137, 2015. [76] L. Tang, Y. K. Joshi, "A Multi-Grid Based Multi-Scale Thermal Analysis Approach for Combined Mixed Convection, Conduction, and Radiation Due to Discrete Heating," ASME Journal of Heat and Mass Transfer, vol. 127, 2005. [77] Y. C. Chen, "Domain Decomposition Method for Steady-State Thermal Analysis with Multiscale Technique," Master's Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan, 2025 [78] Cimrman, R., Lukeš, V. & Rohan, E. "Multiscale finite element calculations in Python using SfePy," Advances in Computational Mathematics, vol. 45, no. 4, pp. 1897-1921, 2019. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99443 | - |
| dc.description.abstract | 現代三維積體電路 (3-D IC) 因垂直堆疊與高功率密度，帶來前所未有的熱管理挑戰。為突破單一全域有限元素分析在百萬級網格上動輒耗盡記憶體的瓶頸，本論文提出一種雙層級域分解方法，實現複雜三維異質介質結構的記憶體高效穩態熱分析。
所提方法將熱分析全域依分層結構劃分為垂直子域，獨立求解各子域同時透過迭代強制介面上的溫度與熱通量連續性。關鍵創新為雙階段求解過程，首先，預求解粗網格全域問題以較少計算資源捕捉整體溫度分布，接著細網格子域問題使用粗解作為初始邊界條件來精修局部熱場。此階層式策略將典型迭代次數從超過50次降至約15-20次。 模擬結果顯示，與傳統有限元素分析相比，記憶體消耗降低71-78%，同時維持節點溫度誤差在0.25%內。此外，框架的模組化設計允許以替代求解器取代有限元素核心，創造與其他工具或神經網路求解器整合的彈性，以進一步提升整體效能。本研究為先進封裝技術的熱分析提供一條實用的途徑，透過將記憶體受限問題轉換為可實行的計算流程，此方法實現異質整合時代中可靠度導向設計所需的前期熱分析架構。 | zh_TW |
| dc.description.abstract | Modern three-dimensional integrated circuits present unprecedented thermal management challenges due to their vertical integration and increased power densities. This thesis develops a two-level domain decomposition method that enables memory-efficient steady-state thermal analysis of complex 3D heterogeneous structures representative of integrated circuit packages. The approach addresses the fundamental limitation of conventional finite element methods, which require prohibitive memory resources when applied to detailed package models containing millions of elements.
The proposed method partitions the thermal domain into vertical subdomains, solving each subdomain independently while iteratively enforcing temperature and flux continuity at interfaces. An innovation is the two-stage solution process, first, a coarse global problem captures the overall temperature distribution using lower computational resources; subsequently, fine-mesh subdomain problems refine local thermal fields using the coarse solution as initial boundary conditions. This hierarchical strategy reduces the typical iteration count from over 50 to approximately 15-20 cycles. Three benchmark cases validate the approach. Across all cases, memory consumption decreases by 71-78% compared to traditional FEM solvers while maintaining temperature accuracy within 0.25%. The framework's modular design allows substitution of the finite element kernel with alternative solvers, creating opportunities for integration with commercial tools or emerging physics-informed neural networks. This work provides a practical pathway for thermal sign-off of advanced packaging technologies. By transforming memory-limited problems into computationally tractable analyses, the method enables early-stage thermal exploration essential for reliability-aware design in the era of heterogeneous integration. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-09-10T16:18:15Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-09-10T16:18:15Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 I
中文摘要 II ABSTRACT III LIST OF CONTENTS V LIST OF FIGURES X LIST OF TABLES XII CHAPTER 1 INTRODUCTION 1 1.1 Background and Motivation 1 1.1.1 Evolution from Planar Scaling to 3D Integration 1 1.1.2 Addressing Memory Constraints in 3D Thermal Analysis 2 1.2 Literature Review 3 1.2.1 Advanced Packaging and Chip Stacking Techniques 3 1.2.2 Numerical Methods for Thermal Analysis 7 1.2.3 Bottlenecks in 3D IC Thermal Simulation 9 1.2.4 Domain Decomposition Method and Two-level Strategies 10 1.3 Thesis Organization 11 CHAPTER 2 THERMAL MODELING AND FINITE ELEMENT FRAMEWORK FOR 3D HETEROGENEOUS STRUCTURES 13 2.1 Chapter Introduction 13 2.2 Fundamentals of Steady-State Heat Conduction in 3D Problems 13 2.2.1 Conservation of Energy 14 2.2.2 Fourier’s Law and the One-Dimensional Conduction Equation 14 2.2.3 Boundary Condition Topology 15 2.2.4 Generalization of Layered Three-Dimensional IC Structures 16 2.2.5 Relevance to 3D IC Analysis 17 2.3 Tile-Based Geometric Modeling 18 2.4 Finite Element Method 19 2.4.1 Rationale and Overall Workflow of the Finite-Element Analysis 19 2.4.2 Variational Formulation of the Governing Equation 21 2.4.3 Element Discretization and Shape Functions 21 2.4.4 Imposition of Boundary Conditions 23 2.4.5 Global Assembly of the Finite Element System 26 2.5 Mesh Generation and Solver Implementation with Gmsh and SfePy 28 CHAPTER 3 TWO-LEVEL DOMAIN-DECOMPOSITION METHOD FOR 3D THERMAL ANALYSIS 30 3.1 Chapter Introduction 30 3.2 Introduction to Domain-Decomposition Methods 31 3.2.1 Mathematical Foundation of Domain Decomposition 32 3.2.2 Interface Conditions and the Schur Complement System 33 3.2.3 Iterative Solution Strategy 34 3.3 Domain Partitioning Strategy for Thermal Analysis 35 3.3.1 Tile-Based Domain Partitioning 36 3.3.2 Interface Node Identification 38 3.4 Two-level Neumann-Neumann Algorithm 39 3.4.1 Coarse-Grid Initialization Strategy 40 3.4.2 Fine-Scale Neumann-Neumann Iteration for Steady-State Heat Transfer 42 3.4.3 Interface Temperature Update with Richardson Iteration 47 3.4.4 Convergence Analysis 48 3.5 Program Implementation Details and Parameters 50 3.5.1 Implementation Overview 51 3.5.2 Model Generation and Mesh Preparation 53 3.5.3 Finite Element Solver Integration 55 3.5.4 Domain Decomposition Implementation 57 CHAPTER 4 NUMERICAL EXPERIMENTS AND RESULTS 61 4.1 Chapter Introduction 61 4.2 Experimental Setup 62 4.2.1 Test Case Configuration 62 4.2.2 Computational Environment 69 4.3 Simulation Results 69 4.3.1 Temperature Distribution and Error Analysis 70 4.3.2 Memory Usage and Runtime Analysis 80 CHAPTER 5 CONCLUSION AND FUTURE WORK 84 5.1 Conclusion 84 5.2 Future Work 86 5.2.1 Lateral Domain Decomposition for Heterogeneous Integration 86 5.2.2 Physics-Informed Neural Networks as Subdomain Solvers 87 REFERENCES 88 A. CoWoS 88 B. InFO 89 C. SoIC 91 D. Numerical Methods for Thermal Analysis 92 E. Bottlenecks in 3-D IC Thermal Simulation 94 F. Domain Decomposition Method and Two-level Strategies 95 G. Thermal Modeling and Simulation Techniques 96 H. DDM 99 I. Finite Element Method Implementation 101 | - |
| dc.language.iso | en | - |
| dc.subject | 域分解法 | zh_TW |
| dc.subject | 三維積體電路 | zh_TW |
| dc.subject | 熱模擬 | zh_TW |
| dc.subject | 有限元素法 | zh_TW |
| dc.subject | Finite Element Method | en |
| dc.subject | 3DIC | en |
| dc.subject | Thermal Simulation | en |
| dc.subject | Domain Decomposition Method | en |
| dc.title | 應用於3D異質介質穩態熱分析之雙層級域分解方法 | zh_TW |
| dc.title | Two-Level Domain-Decomposition Method for Steady-State Thermal Analysis of 3D Heterogeneous Media | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.coadvisor | 鄭士康 | zh_TW |
| dc.contributor.coadvisor | Shyh-Kang Jeng | en |
| dc.contributor.oralexamcommittee | 陳偉倫;陳柏羽 | zh_TW |
| dc.contributor.oralexamcommittee | Woei-Luen Chen;Po-Yu Chen | en |
| dc.subject.keyword | 有限元素法,域分解法,熱模擬,三維積體電路, | zh_TW |
| dc.subject.keyword | Finite Element Method,Domain Decomposition Method,Thermal Simulation,3DIC, | en |
| dc.relation.page | 101 | - |
| dc.identifier.doi | 10.6342/NTU202503022 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-08-05 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 積體電路設計與自動化學位學程 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 積體電路設計與自動化學位學程 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-113-2.pdf 未授權公開取用 | 4.26 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。