一種以CMOS製程實現的緊湊無電容QPSK收發機

Abstract

現代記憶體介面多採用點對點傳輸以支援高速資料傳輸需求，但也伴隨接腳數量與功耗增加等挑戰。相較之下，多點(multi-drop)記憶體通道具備成本與擴充性優勢，然而其頻寬與訊號完整性問題使設計變得更加困難。 本研究提出一種基於QPSK調變的收發器架構，從電路上取代了接收端濾波器中的大電容元件，以降低硬體複雜度與晶片面積。該架構目標運作於1.5 GHz時脈與總計1.5 Gbps資料速率，應用於高效率記憶體介面，以兼顧接收端簡化與頻譜效率提升。雖然實作版本尚未於預定操作條件下成功驗證，但於降頻操作下已完成功能正確性測試，顯示其在簡化接收器設計方面的可行性。 所提出的收發機架構以TSMC 0.18 μm CMOS製程實現，在1 GHz時脈與總計1 Gbps的資料速率下，成功完成QPSK訊號的傳送與解調，整體功耗為14.62 mW。其中接收端功耗僅為3.02 mW，晶片面積為0.0051 mm2。 此成果可為未來高整合度、多通道記憶體系統提供設計參考，並具潛力透過後續電路優化實現更高速之操作目標。

Modern memory interfaces typically adopt point-to-point topologies to support high data rates, but this approach leads to increased pin count and power consumption. In contrast, multi-drop memory channels offer advantages in cost and scalability; however, their bandwidth and signal integrity issues complicate the design significantly. This work proposes a QPSK-based transceiver architecture that replaces large capacitors in the receiver's filter circuit, thereby reducing hardware complexity and chip area. This architecture aims to operate at a 1.5 GHz clock frequency with a aggregrate data rate of 1.5 Gbps, targeting high-efficiency memory interfaces to balance receiver simplification and spectral efficiency enhancement. Although the implemented version has not yet been successfully verified under the intended operating conditions, its behavioral accuracy has been confirmed under reduced clock frequency operation, demonstrating its feasibility in simplifying receiver design. The proposed transceiver was implemented in TSMC 0.18 μm CMOS and successfully transmitted and demodulated QPSK signals at 1 GHz clock and 1 Gbps aggregrate data rate, with a power consumption of 14.62 mW. The receiver core consumes only 3.02 mW and occupies 0.0051 mm2 of silicon area. The results provide valuable insights for the development of future high-density, multi-channel memory systems, and the design shows promise for future enhancement toward higher-speed operation.