應用於控制量子位元之低溫CMOS類比前端電路

Abstract

本論文提出一個應用於控制量子位元的類比前端控制電路之設計與實現，該電路採用台積電40奈米 CMOS 製程進行製作。此前端電路包含超源極跟隨器架構濾波器與可變增益放大器，目標為在低溫環境下達成高保真度、低功耗及寬頻操作的性能要求。 基於超源極跟隨器架構之濾波器實現一個二階低通轉換函數，其-3 dB頻寬達到400 MHz，同時在1 V 電源下保持42.8 dB的信噪比與-50.4 dB的總諧波失真，同時功耗僅為0.057毫瓦特。該濾波器的擬差動架構消除了對共模回授電路的需求，提升了功率效率與線性度。 可變增益放大器採用自補償電晶體與主動電感進行頻寬延展，實現了35.4 dB的增益調變範圍，並可操作至1 GHz。設計展現出精確的dB 線性特性，同時功耗僅為0.438毫瓦特。 實驗驗證部分，晶片透過鍵合線連接至自行設計的印刷電路板進行量測，所使用的儀器包括示波器、信號產生器與頻譜分析儀等。晶片實拍顯示，總面積為1.109 × 1.011 mm²，核心電路面積為0.046 mm²。量測結果證實，所提出之設計達到了量子信號控制所需的嚴格性能要求，具備高保真度、寬頻操作及低功耗等特性。

This thesis presents the design and implementation of an analog front-end control circuit for qubit control, fabricated using TSMC 40-nm CMOS technology. The front-end includes a Super-Source-Follower (SSF)-based filter and a Variable Gain Amplifier (VGA), targeting high fidelity, low power, and wide bandwidth operation in cryogenic environments. The SSF-based filter achieves a second-order low-pass transfer function , achieving a -3 dB bandwidth of 400 MHz. Under a 1 V power supply, it maintains a signal-to-noise ratio (SNR) of 42.8 dB and a total harmonic distortion (THD) of -50.4 dB, while power consuming only 0.057 mW. Its pseudo-differential architecture eliminates the need for a common-mode feedback circuit, improving power efficiency and linearity. The VGA, designed with self-compensated transistors and active inductors for bandwidth extension, provides a gain variation range of 35.4 dB and operates up to 1 GHz. The design demonstrates precise dB-linear characteristics while consuming 0.438 mW. Experimental validation was performed with the chip bonded to a custom-designed PCB, using measurement instruments such as oscilloscopes, signal generators, and spectrum analyzers. The die photo shows a total area of 1.109 × 1.011 mm², with a core circuit area of 0.046 mm². Measurement results confirm that the proposed design meets the stringent requirements for quantum signal control, achieving high fidelity, wide bandwidth, and low power consumption.