一種具有誤差抵消技術之參考電壓緩衝電路用於次區間連續漸進式類比至數位轉換器

Abstract

近年來，行動載具已完全融入人們的生活之中，而在其無線通訊模組裡，連續漸進式類比至數位轉換器扮演著將射頻訊號數位化的關鍵角色，而連續漸進式類比至數位轉換器的性能極為依賴穩定的電源供應，因為電源波動會直接影響其轉換的精確度以及對雜訊的表現。 本論文結合了誤差抵消技術與複製級反向電壓跟隨器，以優化次區間連續漸進式類比至數位轉換器的性能。誤差抵消技術透過校正瞬態誤差來加速電容式數位至類比轉換器的穩定過程，確保高速且精確的轉換。同時，複製級反向電壓跟隨器提供高效的緩衝能力，並顯著降低功耗與電路面積需求。此類比至數位轉換器利用安定時間緩解的技巧降低電容式數位至類比轉換器穩定的需求，藉此提升類比至數位轉換器的取樣頻率，同時透過誤差校正技術補償次區間類比至數位轉換器之間的不匹配。該晶片採用台積電的TSMC 45nm CMOS Logic General Purpose Superb（40G）ELK Cu 1P10M製程實現，在每秒三億四千萬取樣頻率下操作、十萬輸入頻率時，測得有效位元數為7.03 bits，訊號雜訊比為46.84 dB，總諧波失真為-47.37 dB，無失真動態範圍為58.98 dB，訊號雜訊失真比為44.09 dB。整體功耗為2.1 mW，Walden品質因數為29.2 fJ/step。

Mobile devices have become an integral part of daily life in recent years, with SAR ADCs playing a critical role in digitizing RF signals within wireless communication modules. However, the performance of SAR ADCs heavily depends on a stable power supply, as fluctuations can directly impact conversion accuracy and noise performance. This thesis integrates error cancellation and the replica-stage flipped voltage follower to optimize a subranging SAR ADC. Error cancellation accelerates C-DAC settling by correcting transient errors, ensuring high-speed and precise conversions. Meanwhile, the replica-stage flipped voltage follower ensures efficient buffering with reduced power and area. The ADC employs settling time relief techniques to reduce the stability requirements of the C-DAC, thereby increasing sampling speed. Error correction techniques are also applied to compensate for mismatches between subranging ADCs. Fabricated using TSMC’s 45nm CMOS Logic General Purpose Superb (40G) ELK Cu 1P10M process, the ADC operates at 340MS/s with a 100kHz input frequency, achieving an ENOB of 7.03, SNR of 46.84 dB, THD of -47.37 dB, SFDR of 58.98 dB, and SNDR of 44.09 dB. The total power consumption is 2.1 mW, with a Walden FoM of 29.2 fJ/step.