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| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | zh_TW |
| dc.contributor.advisor | Hsin-Shu Chen | en |
| dc.contributor.author | 高致浩 | zh_TW |
| dc.contributor.author | Chih-Hao Kao | en |
| dc.date.accessioned | 2025-02-27T16:36:43Z | - |
| dc.date.available | 2025-02-28 | - |
| dc.date.copyright | 2025-02-27 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-02-11 | - |
| dc.identifier.citation | [1]P. Harikumar et al., "Design of a Reference Voltage Buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS," in Proc. IEEE Int. Symp. Circuits and System, pp. 249–252, May 2015.
[2]T.-Y. Man, et al., "Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 5, Apr. 2008. [3]Mo Huang et al., "An Analog-Assisted Tri-loop Digital Low-Dropout Regulator," in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, Jan. 2018. [4]X. Ma, et al., "An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS, " in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 4041-4052, Nov. 2020. [5]Y. S. Hu et al., "A 0.6 V 6.4 fJ/conversion-step 10-bit 150 MS/s Subranging SAR ADC in 40 nm CMOS," IEEE Asian Solid-State Circuits Conference, pp. 81-84, 2014. [6]C.-C. Liu et al., ”A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010. [7]W. C. Black, Jr., and D. A. Hodges, “Time interleaved converter arrays,” IEEE J.Solid-State Circuits, vol. SC-15, no. 6, pp. 1022–1029, Dec. 1980. [8]C. -H. Chan et al., "60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration," in IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2576-2588, Oct. 2017. [9]M. Huang, H. Feng and Y. Lu, "A Fully Integrated FVF-Based Low-Dropout Regulator With Wide Load Capacitance and Current Ranges," in IEEE Transactions on Power Electronics, vol. 34, no. 12, pp. 11880-11888, Dec. 2019. [10]C. Liu, et al., "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [11]B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC", IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739- 747, Apr. 2007. [12]V. Hariprasath, et al., “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” IEEE Electronics Letters, vol. 46, no. 9, pp. 620-621, Apr. 2010. [13]B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier," IEEE Journal of Solid-State Circuits, pp. 1148-1158, July. 2004. [14]M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s," in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [15]Shuo-Wei Mike Chen and R. W. Brodersen, "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13/spl mu/m CMOS," in IEEE ISSCC Dig. Tech. Papers, pp. 2350-2359, Feb. 2006. [16]C. Lee, et al., "A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 9, Apr. 2013. [17]J. Ramirez-Angulo, A. Torralba, J. Galan, A. P. Vega-Leal, and J. Tombs, "Low-power low-voltage analog electronic circuits using the flipped voltage follower," in Proc. IEEE Int. Symp. Ind. Electron., Jul. 2002, pp. 1327–1330. [18]J. Ramirez-Angulo, R. G. Carvajal, A. Torralba, J. Galan, A. P. Vega-Leal, and J. Tombs, "The flipped voltage follower: A useful cell for low-voltage low-power circuit design," in Proc. IEEE Int. Sym. Circuits Syst., May 2002, vol. 3, pp. 615–618. [19]J. Ramirez-Angulo, S. Gupta, I. Padilla, R. G. Carvajal, A. Torralba, M. Jimenez, and F. Munoz, "Comparison of conventional and new flipped voltage structures with increased input/output signal swing and current sourcing/sinking capabilities," in Proc. IEEE Int. Sym. Circuits Syst., Aug. 2005, vol. 2, pp. 1151–1154. [20]P. Hazucha, T. Kamik, B. A. Bloechel, C. Parsons, and S. Borkar, "Area-efficient linear regulator with ultra-fast load regulation," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933–940, Apr. 2005. [21]P. R. Surkanti et al., "Flipped Voltage Follower Low Dropout (LDO) Voltage Regulators: A Tutorial Overview," in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems, pp. 232–237. [22]F. Chen, Y. Lu and P. K. T. Mok, "A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-μ V/mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 56, no. 2, pp. 511-520, Feb. 2021. [23]K.-H. Chen, "Power Management Techniques for Integrated Circuit Design," pp. 85-93, Sep. 2016 [24]M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s," in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010 [25]H. S. Bindra, A. -J. Annema, G. Wienk, B. Nauta and S. M. Louwsma, "A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-4, doi: 10.1109/CICC.2019.8780150. [26]K. -J. Moon et al., "A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS," 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017, pp. C94-C95, doi: 10.23919/VLSIC.2017.8008560. [27]Y. -J. Jo, J. E. Kim, K. -H. Baek and T. T. -H. Kim, "A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 9, pp. 3088-3092, Sept. 2021, doi: 10.1109/TCSII.2021.3097126. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97192 | - |
| dc.description.abstract | 近年來，行動載具已完全融入人們的生活之中，而在其無線通訊模組裡，連續漸進式類比至數位轉換器扮演著將射頻訊號數位化的關鍵角色，而連續漸進式類比至數位轉換器的性能極為依賴穩定的電源供應，因為電源波動會直接影響其轉換的精確度以及對雜訊的表現。
本論文結合了誤差抵消技術與複製級反向電壓跟隨器，以優化次區間連續漸進式類比至數位轉換器的性能。誤差抵消技術透過校正瞬態誤差來加速電容式數位至類比轉換器的穩定過程，確保高速且精確的轉換。同時，複製級反向電壓跟隨器提供高效的緩衝能力，並顯著降低功耗與電路面積需求。此類比至數位轉換器利用安定時間緩解的技巧降低電容式數位至類比轉換器穩定的需求，藉此提升類比至數位轉換器的取樣頻率，同時透過誤差校正技術補償次區間類比至數位轉換器之間的不匹配。該晶片採用台積電的TSMC 45nm CMOS Logic General Purpose Superb（40G）ELK Cu 1P10M製程實現，在每秒三億四千萬取樣頻率下操作、十萬輸入頻率時，測得有效位元數為7.03 bits，訊號雜訊比為46.84 dB，總諧波失真為-47.37 dB，無失真動態範圍為58.98 dB，訊號雜訊失真比為44.09 dB。整體功耗為2.1 mW，Walden品質因數為29.2 fJ/step。 | zh_TW |
| dc.description.abstract | Mobile devices have become an integral part of daily life in recent years, with SAR ADCs playing a critical role in digitizing RF signals within wireless communication modules. However, the performance of SAR ADCs heavily depends on a stable power supply, as fluctuations can directly impact conversion accuracy and noise performance.
This thesis integrates error cancellation and the replica-stage flipped voltage follower to optimize a subranging SAR ADC. Error cancellation accelerates C-DAC settling by correcting transient errors, ensuring high-speed and precise conversions. Meanwhile, the replica-stage flipped voltage follower ensures efficient buffering with reduced power and area. The ADC employs settling time relief techniques to reduce the stability requirements of the C-DAC, thereby increasing sampling speed. Error correction techniques are also applied to compensate for mismatches between subranging ADCs. Fabricated using TSMC’s 45nm CMOS Logic General Purpose Superb (40G) ELK Cu 1P10M process, the ADC operates at 340MS/s with a 100kHz input frequency, achieving an ENOB of 7.03, SNR of 46.84 dB, THD of -47.37 dB, SFDR of 58.98 dB, and SNDR of 44.09 dB. The total power consumption is 2.1 mW, with a Walden FoM of 29.2 fJ/step. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-02-27T16:36:43Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-02-27T16:36:43Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II Abstract III Contents V List of Figures VIII List of Tables XII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Reference Buffer Circuit 4 2.1 Introduction 4 2.2 Performance Metrics 5 2.2.1 Transient Response 6 2.2.2 Stability Analysis 9 2.2.3 Line Regulation and Load Regulation 10 2.2.4 Quiescent Current 13 2.2.5 Power Efficiency 13 2.2.6 Power Supply Rejection Ratio (PSRR) 14 2.3 Architectures 15 2.3.1 Analog LDO Regulator 16 2.3.2 Digital LDO Regulator 19 2.3.3 Analog-Assisted Digital LDO Regulator 22 2.3.4 Digital-Assisted Analog LDO Regulator 24 Chapter 3 Fundamentals of Analog-to-Digital Converter (ADC) 25 3.1 Introduction 25 3.2 Performance Metric 25 3.2.1 Static Performance 25 3.2.1.1 Offset Error 26 3.2.1.2 Gain Error 26 3.2.1.3 Differential and Integral Nonlinearity 27 3.2.2 Dynamic Performance 29 3.2.2.1 Signal-to-Noise Ratio (SNR) 29 3.2.2.2 Total Harmonic Distortion (THD) 30 3.2.2.3 Spurious-Free Dynamic Range (SFDR) 31 3.2.2.4 Signal-to-Noise and Distortion Ratio (SNDR) 31 3.2.2.5 Effective Number of Bits (ENOB) 32 3.2.2.6 Figure of Merit (FoM) 32 3.3 Architectures 33 3.3.1 Successive-Approximation-Register(SAR) 33 3.3.2 Pipeline 35 3.3.3 Two-Step and Sub-Ranging 36 3.3.4 Flash ADC 38 3.3.5 Time-interleaved ADC 39 3.4 Capacitor Switching Algorithm 41 3.4.1 Monotonic Switching 42 3.4.2 Split-capacitor Switching 43 3.4.3 Vcm-based Switching 44 Chapter 4 Reference Buffer for a Subranging SAR ADC 46 4.1 Introduction 46 4.2 Proposed Architecture 47 4.3 Reference Buffer Architecture 49 4.3.1 Replica-Stage Flipped Voltage Follower 49 4.3.2 Error Cancellation Technique 53 4.4 Subranging SAR ADC Architecture 57 4.4.1 Settling Time Relief Technique 57 4.4.2 Error Correction Technique 59 4.4.3 Bootstrapped Circuit 61 4.4.4 Comparator Circuit 63 4.4.4.1 Speed 64 4.4.4.2 Noise 66 4.3.4.3 Offset 68 4.4.5 C-DAC 69 4.4.6 SAR Digital Logic 72 4.5 Simulation Result 74 4.5.1 Pre-layout Simulation 74 4.5.2 Post-layout Simulation 78 Chapter 5 Experimental setup and results 80 5.1 Measurement Setup 80 5.2 Measurement Results 84 5.3 Measurement Discussion 89 Chapter 6 Conclusion and Future Work 92 6.1 Conclusion 92 6.2 Future Work 93 Bibliography 94 | - |
| dc.language.iso | en | - |
| dc.subject | 誤差消除 | zh_TW |
| dc.subject | 次區間 | zh_TW |
| dc.subject | 反向電壓跟隨器 | zh_TW |
| dc.subject | 複製驅動型 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 類比至數位轉換器 | zh_TW |
| dc.subject | 參考電壓緩衝電路 | zh_TW |
| dc.subject | replica-driving | en |
| dc.subject | successive-approximation register (SAR) | en |
| dc.subject | analog-to-digital converter (ADC) | en |
| dc.subject | reference buffer | en |
| dc.subject | error cancellation | en |
| dc.subject | subranging | en |
| dc.subject | flipped voltage follower (FVF) | en |
| dc.title | 一種具有誤差抵消技術之參考電壓緩衝電路用於次區間連續漸進式類比至數位轉換器 | zh_TW |
| dc.title | A Reference Buffer with Error Cancellation Technique for a Subranging SAR ADC | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 鍾勇輝;林宗賢;胡耀升 | zh_TW |
| dc.contributor.oralexamcommittee | Yung-Hui Chung;Tsung-Hsien Lin;Yao-Sheng Hu | en |
| dc.subject.keyword | 連續漸進式,類比至數位轉換器,參考電壓緩衝電路,誤差消除,次區間,反向電壓跟隨器,複製驅動型, | zh_TW |
| dc.subject.keyword | successive-approximation register (SAR),analog-to-digital converter (ADC),reference buffer,error cancellation,subranging,flipped voltage follower (FVF),replica-driving, | en |
| dc.relation.page | 98 | - |
| dc.identifier.doi | 10.6342/NTU202500540 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2025-02-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2025-02-28 | - |
| Appears in Collections: | 電子工程學研究所 | |
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| File | Size | Format | |
|---|---|---|---|
| ntu-113-1.pdf | 4.64 MB | Adobe PDF | View/Open |
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