Skip navigation

DSpace JSPUI

DSpace preserves and enables easy and open access to all types of digital content including text, images, moving images, mpegs and data sets

Learn More
DSpace logo
English
中文
  • Browse
    • Communities
      & Collections
    • Publication Year
    • Author
    • Title
    • Subject
    • Advisor
  • Search TDR
  • Rights Q&A
    • My Page
    • Receive email
      updates
    • Edit Profile
  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96796
Title: 應用於液晶驅動器且具軌對軌B類插值放大器的高線性度十位元數位類比轉換器
A Highly Linear 10-Bit Digital to Analog Converter with Rail-to-Rail Class-B Interpolation Amplifier for LCD Drivers
Authors: 謝律紳
Lu-Shen Shie
Advisor: 陳中平
Chung-Ping Chen
Keyword: 數位轉類比轉換器,電壓插補,低功耗,高解析度,
digital to analog converter,voltage interpolation,low power consumption,high-resolution,
Publication Year : 2024
Degree: 碩士
Abstract: 數位轉類比轉換器(DAC)在許多現代電子系統中扮演著關鍵角色,特別是在數據轉換、信號處理和各類精密控制應用中。本研究旨在設計和實現一種高解析度、低功耗的10位元DAC,以滿足各種對精度和功耗有嚴格要求的應用需求,如音頻處理、傳感器訊號處理、通訊系統、有機發光二極體(OLED) 和液晶顯示器(LCD)。本研究首先探討了傳統DAC架構的優劣,並提提出了一種改進的雙階段架構設計,以提高轉換精度和效率。該設計透過粗調電阻串數位類比轉換器架構及電壓插補技術,實現了對輸出電壓範圍的精確控制,旨在降低DAC的積分非線性誤差(INL)和微分非線性誤差(DNL)。最後使用TSMC 0.18μm Mixed Signal 1P6M製程實現10位元DAC之設計,量測結果顯示其在僅118μW功耗下仍能保持優異的線性度和單調性,展現出其在廣泛電子應用中的潛力。
The digital to analog converter (DAC) is pivotal in numerous modern electronic systems, particularly in data conversion, signal processing, and precision control applications. This study aims to design and implement a high-resolution, low-power 10-bit DAC to meet the stringent accuracy and power consumption requirements of applications such as audio processing, sensor signal conditioning, communication systems, organic light-emitting diodes (OLED), and liquid crystal displays (LCD). The research first evaluates the strengths and limitations of traditional DAC architectures and proposes an enhanced two-stage design to improve conversion accuracy and efficiency. The proposed design leverages a coarse resistor string DAC architecture and voltage interpolation techniques to control the output voltage range precisely, targeting the reduction of integral non-linearity (INL) and differential non-linearity (DNL) in the DAC. The 10-bit DAC was implemented using the TSMC 0.18μm mixed signal 1P6M process, with measurement results demonstrating that the design maintains excellent linearity and monotonicity with a power consumption of just 118 μW, highlighting its potential for a broad range of electronic applications.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96796
DOI: 10.6342/NTU202404770
Fulltext Rights: 未授權
metadata.dc.date.embargo-lift: N/A
Appears in Collections:電子工程學研究所

Files in This Item:
File SizeFormat 
ntu-113-1.pdf
  Restricted Access
14.89 MBAdobe PDF
Show full item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

社群連結
聯絡資訊
10617臺北市大安區羅斯福路四段1號
No.1 Sec.4, Roosevelt Rd., Taipei, Taiwan, R.O.C. 106
Tel: (02)33662353
Email: ntuetds@ntu.edu.tw
意見箱
相關連結
館藏目錄
國內圖書館整合查詢 MetaCat
臺大學術典藏 NTU Scholars
臺大圖書館數位典藏館
本站聲明
© NTU Library All Rights Reserved