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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平 | zh_TW |
| dc.contributor.advisor | Chung-Ping Chen | en |
| dc.contributor.author | 謝律紳 | zh_TW |
| dc.contributor.author | Lu-Shen Shie | en |
| dc.date.accessioned | 2025-02-21T16:35:30Z | - |
| dc.date.available | 2025-02-22 | - |
| dc.date.copyright | 2025-02-21 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-12-30 | - |
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Jeong, and H.-S. Kim, “An area-efficient 10-bit source-driver ic with lsb-stacked lv-to-hv-amplify dac for mobile oled displays,” IEEE Journal of Solid-State Circuits, vol. 58, no. 11, pp. 3164–3178, 2023. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96796 | - |
| dc.description.abstract | 數位轉類比轉換器(DAC)在許多現代電子系統中扮演著關鍵角色，特別是在數據轉換、信號處理和各類精密控制應用中。本研究旨在設計和實現一種高解析度、低功耗的10位元DAC，以滿足各種對精度和功耗有嚴格要求的應用需求，如音頻處理、傳感器訊號處理、通訊系統、有機發光二極體(OLED) 和液晶顯示器(LCD)。本研究首先探討了傳統DAC架構的優劣，並提提出了一種改進的雙階段架構設計，以提高轉換精度和效率。該設計透過粗調電阻串數位類比轉換器架構及電壓插補技術，實現了對輸出電壓範圍的精確控制，旨在降低DAC的積分非線性誤差(INL)和微分非線性誤差(DNL)。最後使用TSMC 0.18μm Mixed Signal 1P6M製程實現10位元DAC之設計，量測結果顯示其在僅118μW功耗下仍能保持優異的線性度和單調性，展現出其在廣泛電子應用中的潛力。 | zh_TW |
| dc.description.abstract | The digital to analog converter (DAC) is pivotal in numerous modern electronic systems, particularly in data conversion, signal processing, and precision control applications. This study aims to design and implement a high-resolution, low-power 10-bit DAC to meet the stringent accuracy and power consumption requirements of applications such as audio processing, sensor signal conditioning, communication systems, organic light-emitting diodes (OLED), and liquid crystal displays (LCD). The research first evaluates the strengths and limitations of traditional DAC architectures and proposes an enhanced two-stage design to improve conversion accuracy and efficiency. The proposed design leverages a coarse resistor string DAC architecture and voltage interpolation techniques to control the output voltage range precisely, targeting the reduction of integral non-linearity (INL) and differential non-linearity (DNL) in the DAC. The 10-bit DAC was implemented using the TSMC 0.18μm mixed signal 1P6M process, with measurement results demonstrating that the design maintains excellent linearity and monotonicity with a power consumption of just 118 μW, highlighting its potential for a broad range of electronic applications. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-02-21T16:35:30Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-02-21T16:35:30Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements i
摘要ii Abstract iii Contents v List of Figures viii List of Tables xi Chapter 1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter 2 Introduction of Traditional Digital to Analog Converter 4 2.1 Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Ideal Digital to Analog Converter . . . . . . . . . . . . . . . . . . . 5 2.3 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.2 Offset and Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.3 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.3.1 Absolute accuracy . . . . . . . . . . . . . . . . . . . . 8 2.3.3.2 Relative accuracy . . . . . . . . . . . . . . . . . . . . 8 2.3.4 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.4.1 Integral Nonlinearity (INL) Error . . . . . . . . . . . . 9 2.3.4.2 Differential Nonlinearity (DNL) Error . . . . . . . . . 10 2.3.5 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.6 Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.7 Conversion/Sampling Rate . . . . . . . . . . . . . . . . . . . . . . 12 2.3.8 Spurios Free Dynamic Range (SFDR) . . . . . . . . . . . . . . . . 12 2.3.9 Total Harmonic Distortion (THD) . . . . . . . . . . . . . . . . . . 13 2.4 The basic architecture of a Digital-to-Analog Converter . . . . . . . 14 2.4.1 Decoder-Based DAC . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1.1 Resistor-String DAC . . . . . . . . . . . . . . . . . . . 15 2.4.1.2 Folded Resistor-String DAC . . . . . . . . . . . . . . 17 2.4.1.3 Multiple Resistor-String DAC . . . . . . . . . . . . . . 19 2.4.2 Binary-Weighted DAC . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.2.1 Binary-Weighted Resistor DAC . . . . . . . . . . . . . 21 2.4.2.2 R-2R-Based DAC . . . . . . . . . . . . . . . . . . . . 23 2.4.2.3 Charge-Redistribution Switched-Capacitor DAC . . . . 25 2.4.2.4 Current-Steering DAC . . . . . . . . . . . . . . . . . . 27 2.4.3 Thermometer-Code DAC . . . . . . . . . . . . . . . . . . . . . . . 30 2.4.3.1 Thermometer-Code Resistor DAC . . . . . . . . . . . 31 2.4.3.2 Thermometer-Code Current-Steering DAC . . . . . . . 32 2.4.4 Hybrid and Segmented DAC . . . . . . . . . . . . . . . . . . . . . 34 Chapter 3 Design of a Hybrid 10-Bit Digital to Analog Converter 38 3.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3 Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4.1 Coarse Resistor String DAC . . . . . . . . . . . . . . . . . . . . . 46 3.4.2 Multi-Input Interpolation Amplifier . . . . . . . . . . . . . . . . . 49 Chapter 4 Measurement Results 59 4.1 Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 Chip-on-Board Measurement Result . . . . . . . . . . . . . . . . . . 64 Chapter 5 Conclusions 71 References 72 | - |
| dc.language.iso | en | - |
| dc.subject | 高解析度 | zh_TW |
| dc.subject | 低功耗 | zh_TW |
| dc.subject | 電壓插補 | zh_TW |
| dc.subject | 數位轉類比轉換器 | zh_TW |
| dc.subject | high-resolution | en |
| dc.subject | digital to analog converter | en |
| dc.subject | voltage interpolation | en |
| dc.subject | low power consumption | en |
| dc.title | 應用於液晶驅動器且具軌對軌B類插值放大器的高線性度十位元數位類比轉換器 | zh_TW |
| dc.title | A Highly Linear 10-Bit Digital to Analog Converter with Rail-to-Rail Class-B Interpolation Amplifier for LCD Drivers | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 鄭士康;趙昌博 | zh_TW |
| dc.contributor.oralexamcommittee | Shyh-Kang Jeng;Paul C.-P. Chao | en |
| dc.subject.keyword | 數位轉類比轉換器,電壓插補,低功耗,高解析度, | zh_TW |
| dc.subject.keyword | digital to analog converter,voltage interpolation,low power consumption,high-resolution, | en |
| dc.relation.page | 76 | - |
| dc.identifier.doi | 10.6342/NTU202404770 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-12-30 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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