應用於相位陣列收發系統之E頻段相移器、天文接收機之Ka頻段低雜訊放大器與分散式放大器之研究

Abstract

本論文包含三個部分。第一部分是應用於相位陣列收發系統的E頻段四位元具有可調功能之開關式相移器設計與量測結果，使用65奈米金氧半場效電晶體製程。第二部分是應用於天文接收機之Ka頻段極低功耗低雜訊放大器設計與量測結果，使用90奈米金氧半場效電晶體製程。第三部分為應用於天文接收機的超寬頻及低功耗分散式放大器之設計與結果，使用90奈米金氧半場效電晶體製程。 首先是預計應用於300 GHz相位陣列收發系統之相移器，此相移器使用兩種開關式相移架構來實現22.5°、45°、90°與180°，並透過加上一反射式相移架構來達到28°之相位調整。量測結果顯示本論文提出的相移器在63-81 GHz展示了小於3°的方均根(RMS)相位誤差與小於2.5 dB的方均根(RMS)增益誤差。平均插入損耗在全頻段約為-21 dB。輸入反射損耗與輸出反射損耗分別小於-7 dB與-15 dB。此外晶片包含pad總面積為0.49平方毫米，不包含pad的總面積為0.28平方毫米。 第二部分提出應用在天文接收機之Ka頻段極低功耗低雜訊放大器，此電路在輸入端使用了閘源極變壓器回授技術來同時達到阻抗和雜訊匹配，自諧振變壓器匹配技術也被採用於此電路的級間匹配。量測結果顯示本論文提出的低雜訊放大器在35 GHz下有19.1 dB的小訊號增益與3.6 GHz的3 dB頻寬，且在有限的1.4 mW功耗下在37.7 GHz有4.2 dB的雜訊指數，而晶片總面積為0.48平方毫米。 最後一部分提出應用在天文接收機之超寬頻及低功耗分散式放大器，此分散式放大放大器(CDA)串接，並以疊接放大器(cascode amplifier)當作其增益元件，而使用主動終端可變電阻(AVTR)技術可以在不會增加直流功耗與占用晶片面積的情況下達到有效調整增益平坦度。量測結果顯示本論文提出的分散式放大器達到21.8 dB的小訊號增益與30 GHz的3-dB頻寬，並在3-dB頻寬內最低雜訊指數為2.9 dB，而晶片總面積為0.77平方毫米。

This thesis consist of three main parts. The first chpter presents the design and measurement results of an E-band 4-bits switched-type phase shifter with phase adjustment for phased-array transceiver systems, fabricated in a 65-nm CMOS process. The second chapter describes the design and measurement results of an ultra-low power Ka-band low noise amplifier (LNA) for astronomical receivers, fabricated in a 90-nm CMOS process. The last chapter discusses the design and measurement of a wideband and low-power distributed amplifier for astronomical receivers, fabricated in a 90-nm CMOS process. The first part focuses on a phase shifter designed for potential network in a 300 GHz phased-array transceiver system. To generate phase shift of 22.5°, 45°, 90°,and 180°, the proposed phase shifter utilizes of two switched-type phase shifter architectures. Additionally, a reflection-type phase shifter topology is incorporated to achieve a phase adjustment of 28°. The measurement results show that the proposed phase shifter exhibits root mean square (RMS) phase error of less than 3° and RMS gain error of less than 2.5 dB at 63 to 81 GHz. The average insertion loss are measured to be around -21 dB at 63 to 81 GHz. The measured input return loss is better than -7 dB at 63 to 81 GHz, and the measured output return loss is better than -15 dB at 63 to 81 GHz. Furthermore, the total area with pads is 0.49 mm2 (0.735 mm 0.665mm), and the core area of the proposed phase shifter is 0.28 mm2 (0.605 mm 0.465mm). The second part presents an ultra-low power Ka-band low noise amplifier (LNA) designed for astronomical receivers. In order to accomplish noise and impedance matching simultaneously, the circuit uses the gate-source transformer feedback technique at the input matching. The self-resonant transformer matching technique is also utilized for inter-stage matching between second and third stage. The measurement results demonstrate that the proposed low noise amplifier achieves a small signal gain of 19.1 dB at 35 GHz with 3-dB bandwidth of 3.6 GHz. Moreover, the LNA presents a noise figure of 4.2 dB at 37.7 GHz with an ultra-low power consumption of 1.4 mW. The total chip area is 0.48 mm2. The last part presents introduces a wideband and low-power distributed amplifier designed for circuit in astronomical receiver. The distributed amplifier architecture combines cascaded single-stage distributed amplifier (CSSDA) with a conventional distributed amplifier (CDA) in cascaded, utilizing cascade amplifier as its gain unit. The gain flatness can be efficiently adjusted using the active variable termination resistor (AVTR) approach without affecting dc power consumption or chip area occupancy. The measurement results show that the proposed distributed amplifier achieves a small signal gain of 21.8 dB with 3-dB bandwidth of 30 GHz. Additionally, within the 3- dB bandwidth, the minimum noise figure is 2.9 dB. The total chip area is 0.77 mm2.