使用0.5V絕緣體上矽金氧半動態臨限電壓技術設計低功率系統應用

Abstract

本篇論文研究主要是探討在奈米製程的bulk和CMOS技術下，使用動態臨限電壓矽金氧半（Dynamic Threshold MOS ; DTMOS）技術最佳化設計低功率系統的應用。第二章為應用90奈米多重臨界電壓互補式矽金氧半（MTCMOS）技術去實現BP-DTMOS-DT（Bulk PMOS Dynamic Threshold MOS with Dual Threshold）的技術設計最佳化低功率系統的應用。比較使用BP-DTMOS-DT類型的邏輯閘cells元件與BP-DTMOS-DT版本的GDSPOM最佳化一個0.5V 16-bit的乘法器電路，與經由正常HVT/LVT類型的邏輯閘cells元件與GDSPOM最佳化後的乘法器電路，在操作頻率為250MHz的條件下，前者可以減少22%的靜態功率消耗。第三章為使用SOI結構，去實現使用DTMOS的技術來設計最佳化低功率超大型積體電路系統的應用。使用SOI DTMOS類型的邏輯閘cells元件經由SOI DTMOS版本GDSPOM程序，最佳化設計一個0.5V 16-bit絕緣體上（SOI）乘法器電路，透過此技術最佳化後的乘法器電路，在滿足操作頻率的條件下，與由全部都使用SOI DTMOS邏輯閘cells元件組成的乘法器電路比較，可以減少30%的功率消耗，第四章為結論和未來研究方向。

This thesis reports DTMOS technique for design optimization of low-power system applications using nanometer bulk and SOI CMOS technologies. In Chapter 2, a 0.5V bulk PMOS dynamic-threshold technique enhanced with dual threshold (MTCMOS): BP-DTMOS-DT for design optimization of low-power system application using 90nm multi-threshold CMOS technology is presented. Via the BP-DTMOS type logic cell technique generated by the gate-level dual-threshold static power optimization methodology (GDSPOM) procedure, a 0.5V 16-bit multiplier circuit has been designed and optimized, showing a reduction of in 22% static power at the operating frequency of 250MHz as compared to the conventional HVT/LVT type counterpart optimized by the GDSPOM reported before. In Chapter 3, a 0.5V SOI CMOS dual-threshold circuit technique via DTMOS is explained for design optimization of low-power VLSI system applications. Via the DTMOS technology for implementing the SOI version of the GDSPOM, a 16-bit SOI multiplier circuit has been designed, showing a performance with 30% less power consumption as compared to the one designed purely in DTMOS, at VDD = 0.5V.