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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Chih-Hsiang Lin | en |
| dc.contributor.author | 林志祥 | zh_TW |
| dc.date.accessioned | 2021-05-20T20:18:23Z | - |
| dc.date.available | 2014-04-29 | |
| dc.date.available | 2021-05-20T20:18:23Z | - |
| dc.date.copyright | 2009-07-14 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-06-26 | |
| dc.identifier.citation | [1] J.B. Kuo, J. Lou, 'Low-Voltage CMOS VLSI Circuits,' Wiley, New York,1999.
[2] S. Chou, “Integration and innovation in the nanoelectronics era,” IEEE International Solid-State Circuits Conference, vol. 1, pp. 36-41, Feb. 2005. [3] G .E. Moore, 'Progress in Digital lntegrated Electronics,' International Electron Devices Meeting, Vol. 21, pp. 11-13, 1975. [4] ITRS, 'ITRS 2004 Update Documents for Review,' http://www.itrs.net/Links/2004Update/2004Update.htm. [5] A. Bellaouar, M. I. Elmasry,“Low-Power Digital VLSI Design：Circuits and System,”Kluwer,1996. [6] ITRS,“ITRS 2001 Documents for Review,”http://www.itrs.net/Links/2001UTRS/Home.htm [7] Power Modelling and Leakage Reduction, 'http://eda.ee.ucla.edu/ EE201A-04Spring/leakage~pres.ppt' [8] T. Douseki, S. Shigematsu, J. Yamada, M. Harada, H. Inokawa, and T. Tsuchiya, “A 0.5V MTCMOS/SIMOX Logic Gate,” IEEE J. Solid-State Circuits, Vol. 32, No. 10, pp. 1604-1609, 1997. [9] S. Shigematsu, S. Muthoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits,” IEEE J. Solid-State Circuits, Vol. 32, No. 6, pp. 861-869, 1997. [10] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,” IEEE Trans. Electron Devices, Vol. 44, No. 3, pp. 414-422, 1997. [11] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi, and Y. Taur, “Channel Profile Optimization and Device Design for Low-Power High-Performance Dynamic- Threshold MOSFET,” IEDM Digest, pp. 113-116, 1996. [12] J. B. Kuo and K. W. Su, “CMOS VLSI Engineering: Silicon-on-Insulator (SOI),' Kluwer: Dordrecht, 1998. [13] W. M. Huang, K. Papworth, M. Racanelli, J. P. John, J. Foerstner, H. C. Shin, H. Park, B. Y. Hwang, T. Wetteroth, S. Hong, H. Shin, S. Wilson and S. Cheng, “TFSOI CMOS Technology for Sub-1V Microcontroller Circuits,” IEDM Dig., pp. 148-151, 1986. [14] Y. Yamaguchi and Y. Inoue, “SOI DRAM: Its Features and Possibilty,” SOI Conf. Dig., pp. 122-124, 1995. [15] Y. Sato, Y. Kado, T. Tsuchiya, T. Kosugi, H. Ishii, and K. Nishimura, “300KG Gate-Array LSI using 0.25um Ultra-Thin-Film Fully-Depleted CMOS/SIMOX with Tungsten-Deposited Source/Drain,” SOI Conf. Dig., pp. 168-169, 1997. [16] 'Power Compiler User Guide,'2007,03. [17] S. Mukhopadhyay, K. Roy, 'Leakage Estimation and Leakage Control for Nano-Scale CMOS Circuits,' Design Automation Conference, 2004. [18] J.B. Kuo, 'CMOS Digital IC,' McGraw-Hill, Taiwan, 1996. [19] R.X. Gu, M.I. Elmasry, 'Power dissipation analysis and optimization of deep submicron CMOS digital circuits,' IEEE Journal of Solid-state Circuits, Vol. 31, lssue 5, pp. 707-71 3, May 1996. [20] J. B. Kuo,“Low-Voltage SOI CMOS Devices and Circuits,” Wiley, New York, 2004. [21] Usami, K., Kawabe, N., Koizuki, M., Seta, K., Furusawa, T.“Automated Selective Multi-Threshold Design for Ultra-Low Standby Applications,”Low Power Electronics and Design Conf Proc, pp. 202-206, 2002. [22] Kao, J., Narendra, S., Chandrakasan, A.“MTCNMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Pattern,”Design Automation Conf. Proc, pp. 495-500, 1998. [23] B. Chung and J.B. Kuo, 'Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application' [24] Shen, E, Kuo, J. B.“A Novel 0.8V BP-DTMOS Content Addressable Memory Cell Circuit Derived from SOI-DTMOS Techniques.” IEEE Conf Elec Dev and Solid State Ckts, pp. 243-245, 2003. [25] Shen, E, Kuo, J. B.“0.8V CMOS CAM Cell Circuit with a Fast Tag-Compare Capability Using Bulk PMOS Dynamic-Threshold (BP-DTMOS) Technique Based on Standard CMOS Technology for Low-Voltage VLSI Systems,” IEEE International Symp. Circuits and Systems Proc, IV 583-586, 2002. [26] Wallace, C.S.“A Suggestion for a Fast Multiplier. IEEE Trans Comput.”, pp. 14-17, 1964. [27] Synopsys, 'Virtuoso Layout Editor User Guide,' ~2005.12. [28] Synopsys, 'Virtuoso Layout XL Editor User Guide,' ~2005.12. [29] Synopsys, 'Design Compiler User Guide,' ~2007.03 [30] Synopsys, 'PrimeTime User Guide,' ~2007.06. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9343 | - |
| dc.description.abstract | 本篇論文研究主要是探討在奈米製程的bulk和CMOS技術下，使用動態臨限電壓矽金氧半（Dynamic Threshold MOS ; DTMOS）技術最佳化設計低功率系統的應用。第二章為應用90奈米多重臨界電壓互補式矽金氧半（MTCMOS）技術去實現BP-DTMOS-DT（Bulk PMOS Dynamic Threshold MOS with Dual Threshold）的技術設計最佳化低功率系統的應用。比較使用BP-DTMOS-DT類型的邏輯閘cells元件與BP-DTMOS-DT版本的GDSPOM最佳化一個0.5V 16-bit的乘法器電路，與經由正常HVT/LVT類型的邏輯閘cells元件與GDSPOM最佳化後的乘法器電路，在操作頻率為250MHz的條件下，前者可以減少22%的靜態功率消耗。第三章為使用SOI結構，去實現使用DTMOS的技術來設計最佳化低功率超大型積體電路系統的應用。使用SOI DTMOS類型的邏輯閘cells元件經由SOI DTMOS版本GDSPOM程序，最佳化設計一個0.5V 16-bit絕緣體上（SOI）乘法器電路，透過此技術最佳化後的乘法器電路，在滿足操作頻率的條件下，與由全部都使用SOI DTMOS邏輯閘cells元件組成的乘法器電路比較，可以減少30%的功率消耗，第四章為結論和未來研究方向。 | zh_TW |
| dc.description.abstract | This thesis reports DTMOS technique for design optimization of low-power system applications using nanometer bulk and SOI CMOS technologies. In Chapter 2, a 0.5V bulk PMOS dynamic-threshold technique enhanced with dual threshold (MTCMOS): BP-DTMOS-DT for design optimization of low-power system application using 90nm multi-threshold CMOS technology is presented. Via the BP-DTMOS type logic cell technique generated by the gate-level dual-threshold static power optimization methodology (GDSPOM) procedure, a 0.5V 16-bit multiplier circuit has been designed and optimized, showing a reduction of in 22% static power at the operating frequency of 250MHz as compared to the conventional HVT/LVT type counterpart optimized by the GDSPOM reported before. In Chapter 3, a 0.5V SOI CMOS dual-threshold circuit technique via DTMOS is explained for design optimization of low-power VLSI system applications. Via the DTMOS technology for implementing the SOI version of the GDSPOM, a 16-bit SOI multiplier circuit has been designed, showing a performance with 30% less power consumption as compared to the one designed purely in DTMOS, at VDD = 0.5V. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-20T20:18:23Z (GMT). No. of bitstreams: 1 ntu-98-R96943094-1.pdf: 2704202 bytes, checksum: 747a3d4566f4885cc0403b2c6e2c40da (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
致謝 iii 中文摘要 iv ABSTRACT v 目錄 vi 圖表 viiii Chapter 1 導論（Introduction） 1 1. 1 互補式矽金氧半超大型積體電路發展的趨勢（CMOS VLSI Trends） 1 1. 2 絕緣體上矽金氧半（SOI MOS） 5 1. 3 功率消耗（Power Consumption） 7 1. 4 論文架構（Thesis Organization） 9 Chapter 2 0.5V Bulk PMOS動態臨限電壓技術使用雙臨界電壓電路最佳化設計低功率90奈米系統應用（0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (BP-DTMOS-DT) Technique for Design Optimization of Low Power 90nm CMOS System Application） 10 2.1 互補式矽金氧半和動態臨限電壓矽金氧半的源由（MTCMOS and DTMOS Trends） 10 2.2 Bulk PMOS動態臨限電壓金氧半元件技術 （BP-DTMOS Technology） 12 2.3 Bulk PMOS動態臨限矽金氧半元件邏輯閘電路（BP-DTMOS-DT Logic Cell） 15 2.4 BP-DTMOS-DT GDSPOM 18 2.5 效能（Performace） 21 2.6 討論（Discussion） 28 Chapter 3 使用0.5V絕緣體上矽金氧半元件動態臨限電壓技術最佳化設計低功率系統應用（0.5V SOI DTMOS Technique for Design Optimization of Low-Power System Applications） 31 3.1 絕緣體上動態臨限電壓矽金氧半元件技術（SOI DTMOS Technlogy） 31 3.2 絕緣體上動態臨限電壓矽金氧半元件邏輯閘電路（SOI DTMOS Logic Cell） 37 3.3 絕緣體上動態臨限電壓矽金氧半元件技術元件資料庫（SOI DTMOS Cell Library） 42 3.4 絕緣體上動態臨限電壓矽金氧半元件GDSPOM（SOI DTMOS GDSPOM） 44 3.5 絕緣體上動態臨限電壓矽金氧半系統應用（SOI DTMOS System） 46 Chapter 4 結論和未來研究方向（Conclusion and Future Work） 53 參考文獻 55 | |
| dc.language.iso | zh-TW | |
| dc.title | 使用0.5V絕緣體上矽金氧半動態臨限電壓技術設計低功率系統應用 | zh_TW |
| dc.title | 0.5V SOI DTMOS Technique for Design Optimization of Low-Power System Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 賴飛羆,陳正雄,蔡成宗,林吉聰 | |
| dc.subject.keyword | 絕緣體上,動態臨限電壓,低功率,低電壓,系統晶片,元件資料庫,多重臨界電壓,乘法器, | zh_TW |
| dc.subject.keyword | SOC,low-power,DTMOS,BP-DTMOS,BP-DTMOS-DT,SOI,SOI DTMOS GDSPOM,0.5V, | en |
| dc.relation.page | 58 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2009-06-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-98-1.pdf | 2.64 MB | Adobe PDF | 檢視/開啟 |
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