研究晶背供電網路架構對奈米片電晶體射頻陣列性能之影響

Abstract

隨著無線通訊技術的演進不斷推動，對更快、更高效能的網路需求越來越迫切。從過去的4G、5G一路演進到即將到來的6G無線通訊，對能夠在從GHz到THz的高頻率範圍內運行的突破性技術需求日益明顯。與此同時，半導體技術的進步如奈米片場效電晶體 （Nanosheet FET, NSFET），在要求嚴格的射頻應用中優於以往的鰭式場效電晶體（FinFET）。具有垂直堆疊通道的奈米片場效電晶體提供了增強的閘極控制和低次臨界擺幅，有助於6G應用的發展。另一方面，隨著電晶體不斷的微縮，在矽基板上方的金屬繞線壅塞問題變得日益嚴峻。近年來晶背供電網路（Backside Power Delivery Network, BSPDN）的設計架構被提出來解決繞線壅塞的問題，透過分離矽基板上方的電源線及接地線，使其與訊號線分開佈局，從而減輕金屬線互連（Interconnect）因微縮所帶來的高互連電阻之挑戰。 本篇論文研究部分底部介電質隔離技術的奈米片場效電晶體應用於射頻陣列（RF array）上。論文首先根據國際元件與系統技術藍圖（International Roadmap for Devices and Systems, IRDS）所提供的結構以及材料參數，透過TCAD模擬軟體建立三維奈米片場效電晶體結構，並與實驗數據校準後段製程銅互連導線之電阻值，本論文研究五種不同架構之射頻陣列，分別為：（1）一般基本的射頻陣列（Baseline RF array）、（2）使用埋入式電源軌架構的射頻陣列（Buried Power Rail RF array, BPR RF array）、（3）使用晶背接觸架構的射頻陣列（Backside Contact RF array, BSC RF array）、（4）同時整合主動元件閘極上接點及埋入式電源軌架構的射頻陣列（Contact Over Active Gate and Buried Power Rail RF array, COAG & BPR RF array）和最後一個（5）同時整合主動元件閘極上接點及晶背接觸架構的射頻陣列（Contact Over Active Gate and Backside Contact RF array, COAG & BSC RF array）。論文首先分析整合晶背供電網路後的邏輯電路，如反向器（Inverter, INV）及環形震盪器（Ring Oscillator, RO）之速度優勢，接著再分析整合晶背供電網路的類比射頻陣列在引入自我加熱效應（Self-heating effect, SHE）影響下之電源電壓降（IR Drop）、截止頻率（Cutoff Frequency, fT）和最大震盪頻率（Maximum Oscillation Frequency, fMAX），研究使用晶背供電網路技術在射頻應用之成效和優勢。 研究結果顯示使用晶背供電網路架構之邏輯電路，不管是在反向器或環形震盪器分別可達到6%-9%及9%-14%的速度優勢。在類比射頻陣列方面，不考慮自我加熱效應的作用下，使用埋入式電源軌架構及晶背接觸之射頻陣列，其電源電壓降分別為52mV及101mV，在fT方面約有25%及51%的提升，而在fMAX方面，將其同時整合主動元件閘極上接點的架構分別有50%和60%的改善。最後，考量自我加熱效應的影響，研究發現其導通電流有下降的趨勢，這也造成在射頻陣列的表現有部分衰退的情形，但研究結果仍可以看到fT在 (1) 晶背接觸(BSC)及 (2) 晶背接觸整合主動元件閘極上接點(COAG & BSC)之射頻陣列仍有1.1倍及1.2倍的提升，而在COAG & BSC的射頻陣列上，由於其大幅降低了閘極阻值（Gate resistance, Rg），因此在fMAX與Baseline陣列相比仍改善35%，提升我們射頻陣列的性能表現。

As wireless communication technologies continue to evolve, the demand for faster and more efficient networks becomes increasingly urgent. From the progression of 4G and 5G to the forthcoming 6G wireless communication, there is a growing need for groundbreaking technologies capable of operating at extraordinary frequencies ranging from GHz to THz. Concurrently, semiconductor advancements, such as Nanosheet FETs (NSFETs), surpass traditional FinFETs in demanding RF applications. NSFETs, with vertically stacked channels, offer enhanced gate control and low sub-threshold swing, positioning them as candidates for 6G applications. However, as transistor scaling progresses, congestion in the metal routing above the silicon substrate becomes increasingly severe. The introduction of Backside Power Delivery Network (BSPDN) architecture offers a solution to alleviate routing congestion by separating the power and signal lines above the silicon substrate, thus mitigating the challenges of reducing interconnect dimensions and reducing the interconnect wire resistance. This thesis utilizes partially bottom dielectric isolation techniques applied to NSFETs in RF arrays. The structures and material parameters used for NSFETs are established based on the International Roadmap for Devices and Systems (IRDS) guidelines, and the copper interconnect wire resistance has been calibrated with the experimental data. In this thesis, five different RF array structures are analyzed, including (1) the Baseline RF array, (2) Buried Power Rail RF array (BPR RF array), (3) Backside Contact RF array (BSC RF array), (4) Contact Over Active Gate, Buried Power Rail RF array (COAG & BPR RF array), and (5) Contact Over Active Gate and Backside Contact RF array (COAG & BSC RF array). The performance advantages of logic circuits, including the inverter (INV) and ring oscillator (RO), integrated with BSPDN are analyzed. This is followed by an assessment of analog RF arrays integrated with BSPDN under self-heating effects (SHE). The research findings show that logic circuits integrated with BSPDN demonstrate speed advantages of 6%-9% for inverters and 9%-14% for ring oscillators. In analog RF arrays, those equipped with BPR exhibit a reduction in IR drop to 52mV, whereas counterparts with BSC experience a reduction to 101mV. These reductions signify approximately 25% and 51% improvements in fT compared to the baseline. On the other hand, when integrated with COAG, significant enhancements in fMAX by 50% and 60% are observed, respectively. However, considering the impact of SHE, there's a decrease in conduction current, leading to some degradation in RF array performance. However, improvements in fT of 1.1x and 1.2x are observed in the RF arrays with (1) BSC and (2) COAG & BSC, respectively, while maintaining advantages of over 35% in fMAX for COAG & BSC RF arrays, enhancing overall RF array performance.