莫列波紋於序列型互補式場效電晶體之垂直對準應用探討

Abstract

過去幾十年來，半導體一直持續遵循著摩爾定律發展，電晶體密度每18個月會加倍。然而，隨著更高效能但體積更小的半導體產品推陳出新，其中的元件晶片在微縮路上反覆面臨物理和技術限制。因此，學研產業各界都持續研究新的技術和晶片結構，以維持摩爾定律引領的半導體增長趨勢。 為了延長摩爾定律同時提升晶片性能，晶片會由傳統平面微縮逐漸朝向3D IC的趨勢發展。3D IC發展方向包含先進封裝技術及新型電晶體立體結構，將多個功能晶片和垂直堆疊的電晶體結構整合在一起，讓晶片朝向立體化發展。其中，在未來技術節點的開發上被高度關注的互補型場效電晶體（CFET）是深具潛力的新型電晶體架構，在此結構中p型與N型電晶體會做垂直堆疊。這種架構可以有效地減少單一電晶體占地面積使電晶體的密度加倍。 序列型互補式場效電晶體(sequential CFET)通常採用晶片鍵合(wafer bonding)等技術，在下層元件上堆疊上層元件的通道材料。此製程方案的其中一項挑戰是製作上層元件時必須考慮熱預算以免影響下層元件的特性，因此發展序列型互補式場效電晶體的低溫整合製程相當重要。本篇論文旨在研究序列型互補式場效電晶體(sequential CFET)方案中垂直堆疊電晶體製程的對準問題，期望發展利用薄膜轉移技術堆疊元件薄膜、完成與下層元件的整合製程。在序列型互補式場效電晶體(sequential CFET)的方案中，我們對曝光圖案佈局設計、堆疊元件層製備和對齊方法進行開發。曝光圖案佈局採用縮小PFET佔地面積以進行金屬層互連，以及設計電晶體布局位置安排以達成垂直堆疊電晶體。 在元件及堆疊製程，我們使用化學機械平坦化及背側矽去除來製備元件薄膜。再以SU-8固定上層元件薄膜，在建立的光學對準系統下進行堆疊，並引入莫列波紋方法來研究兩層電晶體的對準。透過在矽基板和玻璃上製作鉻光柵，我們獲得不同偏差位移的光學莫列波紋，得以評估和校正堆疊層的偏移。最後，我們展示了以莫列波紋方法進行對準堆疊的頂部和底部層電晶體。從實驗結果我們歸納莫列波紋可以作為在可見光下進行結構堆疊的潛力對準方法，有助於實現3D IC中立體堆疊電晶體結構的技術。

Over the decades, the development of semiconductors has followed the pace of Moore’s Law to double the transistor density per 18 months. As semiconductor devices continue to shrink, Moore's Law scaling is encountering inherent physical and technological limitations. Consequently, novel technologies and device structures have been investigated to uphold the growth trajectory outlined by Moore's Law. To extend Moore’ Law and boost the chip performance, 3D IC is a highly pursued trend in future era rather than traditional scaling in the past. 3D IC techniques involve new vertical transistor structures and advanced packaging to integrate multiple function chips and transistor structure in vertical stack. The complementary field effect transistor (CFET) is a potential architecture for 3D development in transistor level and has attracted significant interest. CFET involves stacking a pMOS onto an nMOS or vice versa. This architecture effectively doubles the density of the transistors, leading to a reduction in footprint. The fabrication of sequential CFET typically employs wafer bonding to integrate channel material of top tier devices onto the bottom devices. One of the challenges is the thermal budget to process the top tier devices without degradation in bottom tier devices. Therefore, the low temperature process for sequential CFET is required. In this thesis, we investigate the alignment of vertically stacked transistor experimentally in the developing sequential CFET process which aims at stacking device through membrane transfer techniques. The sequential integration process was developed in mask layout design, device layer preparation for stacking and alignment approach. Mask layout design involves PFET footprint reduction for interconnect and corresponding placement of PFET and NFET. After device fabrication on chip, chemical mechanical planarization, and backside Si stripping were employed to prepare device membrane. In the stacking process, we employed SU-8 to hold the top membrane and implemented Moiré fringe method to investigate the alignment of transistors on two layer. The optical Moiré fringe with various displacement was obtained by fabricating chromium gratings on Si and glass. The misalignment of stacked layer can then be evaluated and calibrated. Finally, we have demonstrated aligned top and bottom tier transistors with Moiré fringe. From the alignment experiment, it is believed that Moiré fringe has potential in providing alignment method under visible light for structure stacking in vertical integration of 3DIC.