一個基於數位時間轉換器的次取樣除小數鎖相迴路

Abstract

本論文介紹了一個操作於5.28 到5.66億赫茲、1450千赫茲頻寬且基於數位至時間轉換器(DTC)的除小數次取樣相位鎖定迴路(SSPLL)，它使用次取樣技術和數位至時間轉換器調變器來實現較低的頻帶內和頻帶外雜訊。由於製程、溫度與電壓的變異，電路運作時須要數位至時間轉換器的增益和線性度的背景校正，以降低非線性雜訊，從而使鎖相迴路獲得更好的性能。數位至時間轉換器將調變參考相位，使次取樣相位偵測器(SSPD)對壓控震盪器(VCO)波形的零交越(zero-crossing)進行取樣，並使鎖相迴路保持鎖定狀態。次取樣相位偵測器的鎖定範圍有限，因此添加了頻率鎖定迴路(FLL)以確保正常運行。此外我使用C-DAC恆定斜率的數位至時間轉換器，因為它比I-DAC恆定斜率的數位至時間轉換器消耗更低的功率。 此鎖相迴路以一個40奈米CMOS製程實現且其主要面積為0.18平方毫米。除電流幫浦(CP)在1.8伏特電源供應下，其他核心電路操作0.9伏特，總功耗為9.3毫瓦，其不包括壓控震盪器輸出緩衝器(VCO buffer)和輸入參考緩衝器(input reference buffer)。操作在5.37億赫茲時測得的相位雜訊在相對於主頻率為100千赫茲和10百萬赫茲時分別達到-97dBc/Hz和-134dBc/Hz。在此載波頻率下，從10千赫茲積分到30百萬赫茲測得的方均根抖動為846毫微微秒。質量因數(FoM)為-231 dB在被提出的基於數位至時間轉換器的除小數次取樣相位鎖定迴路。

This thesis presents a 5.28 - 5.66 GHz, 1450 kHz bandwidth DTC-based fractional-N sub-sampling phase-locked loop (SSPLL) that uses a sub-sampling technique and a DTC modulator to achieve lower in-band and out-of-band noise. Due to the PVT variations, a DTC background calibration which includes gain and INL calibration is needed in the circuits to reduce the non-linearity noise so that the PLL can achieve lower jitter than without calibration. The DTC will modulate the reference phase which makes a sub-sampling phase detector (SSPD) sample a zero crossing of the VCO waveform and keep the PLL in a lock. An SSPD has a limited locking range, so a frequency-locked loop (FLL) is added to ensure proper operation. Additionally, I use the C-DAC constant slope DTC because it consumes lower power than I-DAC constant slope DTC. This PLL is implemented in a TSMC 40-nm 1P9M CMOS process and its active area is 0.18 mm2. Except CP operates under 1.8 V, other core circuits operate under 0.9V and the total power consumption is 9.3 mW excluding the VCO output buffer and input reference buffer. Measured phase noise at 5.37 GHz achieves -97dBc/Hz and -134dBc/Hz at 100-kHz and 10-MHz, respectively. The integrated rms jitter measured from 10-kHz to 30-MHz is 846fs at this carrier frequency. The FoM is -231 dB on the proposed DTC-based sub-sampling fractional-N PLL.