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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91483完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | zh_TW |
| dc.contributor.advisor | Hsin-Shu Chen | en |
| dc.contributor.author | 陳君彥 | zh_TW |
| dc.contributor.author | Juin-Yan Chen | en |
| dc.date.accessioned | 2024-01-28T16:12:11Z | - |
| dc.date.available | 2024-01-29 | - |
| dc.date.copyright | 2024-01-27 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-03-29 | - |
| dc.identifier.citation | [1] IEEE Std 802.11ac™-2013, IEEE Standard for Information technology— Telecommunications and information exchange between systems Local and metropolitan area networks— Specific requirements.
[2] X. Gao, E. Klumperink, P. Geraedts, and B. Nauta, “Jitter analysis and a benchmarking figure-of-merit for phase-locked loops,” IEEE Trans. Circuits Syst. II, vol. 56, no. 2, pp. 117–121, Feb. 2009. [3] M. Perrott, T. Tewksbury, and C. Sodini, “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2048-2060, Dec. 1997. [4] R. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec. 2005. [5] C. Durdodt, M. Friedrich, C. Grewing, M. Hammes, A. Hanke, S. Heinen, J. Oehm, D. Pham-Stabner, D. Seippel, D. Theil, S. Van Waasen, and E. Wag-Ner, "A low-IF RX two-point ΣΔ-modulation TX CMOS single-chip Bluetooth solution," IEEE Trans. Microw. Theory Tech., vol. 49, no. 9, pp. 1531-1537, Sept. 2001. [6] C.-M. Hsu, M. Straayer, and M. Perrott, “A low-noise wide-BW 3.6-GHz digital Δ Σ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2776–2786, Dec. 2008. [7] W. Rhee and A. Ali, “An on-chip phase compensation technique in frequency-N frequency synthesis,” IEEE ISCAS, vol.3, pp. 363-366, 1999. [8] X. Gao, E. Klumperink, M. Bohsali, and B. Nauta, “A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N 2," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3253–3263, Dec. 2009. [9] X. Gao, E. Klumperink, M. Bohsali, and B. Nauta, “Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1809–1821, Sep. 2010. [10] W. S. Chang, P. C. Huang, and T. C. Lee, “A fractional-N divider-less phase-locked loop with a subsampling phase detector,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2964–2975, Dec. 2014. [11] S. Levantino, G. Marucci, G. Marzin, A. Fenaroli, C. Samori, and A. L. Lacaita, “A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2678–2691, Nov. 2015. [12] Z.-Z. Chen, The design and analysis of dual-delay path ring oscillators and a multiphase compensation method for fractional-N frequency synthesizer, Master Thesis, July 2008. [13] C.-H. Park, O. Kim, and B. Kim, “A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching,” IEEE J. Solid-State Circuits, vol. 36, pp. 777-783, May 2001 [14] N. Markulic, K. Raczkowski, P. Wambacq, and J. Craninckximec, “A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS," IEEE ESSCIRC, Nov. 2014. [15] N. Pavlovic and J. Bergervoet, “A 5.3 GHz digital-to-time-converter based fractional-N all-digital PLL,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 20–24, 2011, pp. 54–56. [16] D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori, and A. L. Lacaita, “A 2.9-to-4.0 GHz fractional-N digital PLL with bang-bang phase detector and 560 fsrms integrated jitter at 4.5 mW power,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2011, pp. 88–90. [17] R. B. Staszewski et al., “Spur-free all-digital PLL in 65 nm for mobile phones,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2011, pp. 52–54. [18] M. Safi-Harb and G. W. Roberts, “70-GHz effective sampling time-base on-chip oscilloscope in CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1743–1757, Aug. 2007. [19] T. Okayasu, M. Suda, K. Yamamoto, S. Kantake, S. Sudou, and D. Watanabe, “1.83 ps-Resolution CMOS dynamic arbitrary timing generator for > 4 GHz ATE applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2006. [20] J. Z. Ru, C. Palattella, P. Geraedts, E. Klumperink, and B. Nauta, “A high-linearity digital-to-time converter technique: Constant-slope charging,” IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 1412–1423, Jun. 2015. [21] T. Riley, M. Copeland, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE J. Solid-State Circuits vol. 28, no. 5, pp. 553–559, May 1993. [22] S. Levantino, G. Marzin, C. Samori, and A. Lacaita, “A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration,” IEEE J. Solid-State Circuits vol. 48, no. 10, pp.2419–2429, Oct. 2013. [23] N. Markulic, K. Raczkowski, E. Martens, P.E.P. Filho, B. Hershberg, P. Wambacq, and J. Craninckx, “A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation,” IEEE J. Solid-State Circuits vol. 48, no. 10, pp.2419–2429, Oct. 2013. [24] Ting-Hsu Chien, Chi-Sheng Lin, Chin-Long Wey, and Ying-Zong Juang, “High-Speed and Low-Power Programmable Frequency Divider," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Aug. 2010. [25] L. Fanori and P. Andreani, “Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs,” Solid-State Circuits, IEEE Journal of, vol. 48, no. 7, pp. 1730–1740, July 2013. [26] S. Gagliolo, G. Pruzzo, and D. D. Caviglia, “Phase Noise Performances of a Cross-Coupled CMOS VCO with Resistor Tail Biasing,” Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, Sep.2005. [27] B. Hershberg, K. Raczkowski, K. Vaesen, and J. Craninckx, "A 9.1–12.7 GHz VCO in 28 nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction," in Proc. 40th Eur. Solid-State Circuits Conf. (ESSCIRC), 2014, pp. 83–86. [28] R. Bunch and S. Raman, “Large-signal analysis of MOS varactors in CMOS -Gm LC VCOs,” IEEE J. Solid-State Circuits, vol. 38, pp. 1325-1332, Aug. 2003. [29] H.-Y. Tai, Y.-S. Hu, H.-W. Chen, and H.-S. Chen, “A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS,” in IEEE ISSCC Dig. Papers, Feb. 2014, pp. 196–197. [30] M. Perrott, M. Trott, and C. Sodini, “A modeling approach for Σ – Δ fractional-N frequency synthesizers allowing straightforward noise analysis," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002. [31] N. Markulic, K. Raczkowski, J. Craninckx, and P. Wambacq, Digital subsampling phase lock techniques for frequency synthesis and polar transmission. [32] A. Oppenheim and R. Schafer, Discrete-time signal processing second edition, Prentice Hall, 1999. [33] B. Razavi, RF Microelectronics second edition, Prentice Hall, 2012. [34] M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. S. Choi, and P. K. Hanumolu, “A 5GHz Digital Fractional-N PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS,” Solid-State Circuits, IEEE Journal of, vol. 52, no. 9, pp. 2306–2320, August 2017. [35] A. Li, Y. Chao, X. Chen, L. Wu and H. C. Luong, “A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs,” Solid-State Circuits, IEEE Journal of, vol. 52, no. 8, pp. 2128–2140, April 2017. [36] Q. Zhang, S. Su, C. R. Ho, and M. S. W. Chen, “A Fractional-N Digital MDLL With Background Two-Point DTC Calibration,” Solid-State Circuits, IEEE Journal of, vol. 52, no. 8, pp. 2128–2140, April 2017. [37] C. W. Hsu, K. Tripurari, S. A. Yu, and P. R. Kinget, “A sub-sampling assisted phase-frequency detector for low-noise PLLs with robust operation under supply interference,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 1, pp. 90–99, Jan. 2015. [38] A. T. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K. K. Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa, “A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with an FoM of –250 dB,” Solid-State Circuits, IEEE Journal of, vol. 51, no. 7, pp. 1630–1640, July 2016. [39] K. Raczkowski, N. Markulic, B. Hershberg, and J. Craninckx, “A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS with 280 fs RMS Jitter,” Solid-State Circuits, IEEE Journal of, vol. 50, no. 5, pp. 1203–1213, May 2015. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91483 | - |
| dc.description.abstract | 本論文介紹了一個操作於5.28 到5.66億赫茲、1450千赫茲頻寬且基於數位至時間轉換器(DTC)的除小數次取樣相位鎖定迴路(SSPLL)，它使用次取樣技術和數位至時間轉換器調變器來實現較低的頻帶內和頻帶外雜訊。由於製程、溫度與電壓的變異，電路運作時須要數位至時間轉換器的增益和線性度的背景校正，以降低非線性雜訊，從而使鎖相迴路獲得更好的性能。數位至時間轉換器將調變參考相位，使次取樣相位偵測器(SSPD)對壓控震盪器(VCO)波形的零交越(zero-crossing)進行取樣，並使鎖相迴路保持鎖定狀態。次取樣相位偵測器的鎖定範圍有限，因此添加了頻率鎖定迴路(FLL)以確保正常運行。此外我使用C-DAC恆定斜率的數位至時間轉換器，因為它比I-DAC恆定斜率的數位至時間轉換器消耗更低的功率。
此鎖相迴路以一個40奈米CMOS製程實現且其主要面積為0.18平方毫米。除電流幫浦(CP)在1.8伏特電源供應下，其他核心電路操作0.9伏特，總功耗為9.3毫瓦，其不包括壓控震盪器輸出緩衝器(VCO buffer)和輸入參考緩衝器(input reference buffer)。操作在5.37億赫茲時測得的相位雜訊在相對於主頻率為100千赫茲和10百萬赫茲時分別達到-97dBc/Hz和-134dBc/Hz。在此載波頻率下，從10千赫茲積分到30百萬赫茲測得的方均根抖動為846毫微微秒。質量因數(FoM)為-231 dB在被提出的基於數位至時間轉換器的除小數次取樣相位鎖定迴路。 | zh_TW |
| dc.description.abstract | This thesis presents a 5.28 - 5.66 GHz, 1450 kHz bandwidth DTC-based fractional-N sub-sampling phase-locked loop (SSPLL) that uses a sub-sampling technique and a DTC modulator to achieve lower in-band and out-of-band noise. Due to the PVT variations, a DTC background calibration which includes gain and INL calibration is needed in the circuits to reduce the non-linearity noise so that the PLL can achieve lower jitter than without calibration. The DTC will modulate the reference phase which makes a sub-sampling phase detector (SSPD) sample a zero crossing of the VCO waveform and keep the PLL in a lock. An SSPD has a limited locking range, so a frequency-locked loop (FLL) is added to ensure proper operation. Additionally, I use the C-DAC constant slope DTC because it consumes lower power than I-DAC constant slope DTC.
This PLL is implemented in a TSMC 40-nm 1P9M CMOS process and its active area is 0.18 mm2. Except CP operates under 1.8 V, other core circuits operate under 0.9V and the total power consumption is 9.3 mW excluding the VCO output buffer and input reference buffer. Measured phase noise at 5.37 GHz achieves -97dBc/Hz and -134dBc/Hz at 100-kHz and 10-MHz, respectively. The integrated rms jitter measured from 10-kHz to 30-MHz is 846fs at this carrier frequency. The FoM is -231 dB on the proposed DTC-based sub-sampling fractional-N PLL. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-01-28T16:12:11Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-01-28T16:12:11Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員會審定書 I
致謝 III 摘要 V Abstract VII Contents IX List of Figures XIII List of Tables XVII Chapter 1 Introduction 1 1.1 Motivation and Research Goals 1 1.2 Thesis Organization 5 Chapter 2 Background of Phase-locked Loop (PLL) 7 2.1 Introduction 7 2.2 Sub-sampling Technique 13 2.3 Multiphase Compensation Method in Fractional-N PLL 18 2.4 Digital-to-time Converter (DTC) Application in Fractional-N PLL 23 2.5 Summary 26 Chapter 3 Proposed DTC-based Fractional-N Sub-sampling PLL 27 3.1 Architecture of PLL 28 3.2 Locking Operation 31 3.3 Architecture of C-DAC Constant slope DTC 33 3.4 DTC modulator 38 3.4.1 Block Diagram 38 3.4.2 A Method of DTC Background Gain Calibration 41 3.4.3 A Method of DTC Background INL Calibration 45 3.5 Behavior Model and Simulation 48 3.6 Circuit Implementation 50 3.6.1 Sub-sampling Loop 50 3.6.2 Frequency-locked Loop 55 3.6.2.1 3-state PFD with Dead Zone 56 3.6.2.2 Divider 57 3.6.3 Voltage-controlled Oscillator 60 3.6.4 Loop Filter 64 3.6.5 C-DAC Constant-slope DTC 65 3.6.6 Input/output Buffer 69 3.7 Summary 70 Chapter 4 Noise Model and Simulation Results of the Proposed PLL 72 4.1 Linear Noise 72 4.1.1 Linear Noise Model 73 4.1.2 Linear Phase Noise 75 4.1.2.1 Reference Noise 75 4.1.2.2 DTC Quantization Noise 76 4.1.2.3 Sub-sampling Phase Detector Noise 77 4.1.2.4 Charge Pump Noise 78 4.1.2.5 Loop Filter Resistor Noise 79 4.1.2.6 VCO Noise 79 4.1.2.7 Total Linear Noise 80 4.2 Nonlinear Noise 81 4.2.1 Nonlinear Noise Model 81 4.2.2 DTC Nonlinear Phase Noise 82 4.2.2.1 Gain error 84 4.2.2.2 Gradient error 84 4.2.3 DTC Resolution 85 4.3 All of the Linear and Nonlinear Phase Noise 87 4.4 Circuit Simulation Results 88 4.4.1 DTC Simulation 89 4.4.2 VCO Simulation 91 4.4.3 Overall Transient Simulation 92 4.4.4 Noise and System Simulation 95 4.4.4.1 Reference Noise 95 4.4.4.2 SSPD/CP Noise 96 4.4.4.3 VCO Noise 97 4.4.4.4 LF Noise 98 4.4.4.5 Total Noise and System Analysis 99 4.5 Summary 104 Chapter 5 Experimental Results 105 5.1 Print Circuit Board Design 105 5.2 Measurement Environment 110 5.3 Measurement Results 111 5.3.1 Area and Power Dissipation 112 5.3.2 VCO Tuning Range and Gain 115 5.3.3 Phase Noise and Spurs 116 5.4 Comparison 122 5.5 Summary 124 Chapter 6 Conclusion 125 6.1 Thesis Summary 125 6.2 Future Works 127 Bibliography 129 | - |
| dc.language.iso | en | - |
| dc.subject | 數位至時間轉換器 | zh_TW |
| dc.subject | 除小數鎖相迴路 | zh_TW |
| dc.subject | 次取樣相位鎖定迴路 | zh_TW |
| dc.subject | fractional-N PLL | en |
| dc.subject | sub-sampling phase-locked loop | en |
| dc.subject | digital-to-time converter | en |
| dc.title | 一個基於數位時間轉換器的次取樣除小數鎖相迴路 | zh_TW |
| dc.title | A DTC-based Sub-sampling Fractional-N PLL | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 李泰成;陳筱青 | zh_TW |
| dc.contributor.oralexamcommittee | Tai-Cheng Lee;Hsiao-Chin Chen | en |
| dc.subject.keyword | 次取樣相位鎖定迴路,數位至時間轉換器,除小數鎖相迴路, | zh_TW |
| dc.subject.keyword | sub-sampling phase-locked loop,digital-to-time converter,fractional-N PLL, | en |
| dc.relation.page | 135 | - |
| dc.identifier.doi | 10.6342/NTU202300702 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2023-03-29 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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