一個高速連續漸進式類比至數位轉換器與類比佈局產生器使用參數化單元之可程式化繞線

Abstract

本論文分別有兩個題目，第一個是高速連續漸進式類比至數位轉換器，第二個是參數化單元之可程式化繞線用於類比佈局產生器。 本論文第一個題目提出一個高速連續漸進式類比至數位轉換器，實現於二十八奈米製程，架構上採用次區間類比至數位轉換器，來提高轉換速度，採用安定時間緩解技巧來獲得更多轉換時間，也採用了偵測與迴避演算法來改善線性度及降低切換功耗。 此高速連續漸進式類比至數位轉換器在每秒二億取樣頻率、一千萬輸入頻率時，可以達到八點五三的有效位元，無雜散訊號動態範圍為五十六點二分貝，訊號對雜訊失真比為五十三點一分貝，功耗為一點八毫瓦。而在每秒三億取樣頻率、奈奎斯特一點五億輸入頻率時，可以達到七點四一的有效位元，無雜散訊號動態範圍為五十四點七七分貝，訊號對雜訊失真比為四十六點三五分貝，功耗為二點五毫瓦。 本論文第二個題目提出使用參數化單元之可程式化繞線用於類比佈局產生器，優化包括三個步驟，電晶體創建、保護環創建、對稱技巧，這些優化使得類比佈局生成器能夠生成與自定義佈局相似的佈局，並實現於一個採用四十奈米製程的參考電壓緩衝電路，類比佈局生成器與自定義佈局的面積分別為一百五十點三微米平方及一百四十四點七微米平方。

This thesis consists of two works: the first one is a high-speed SAR ADC, and the second one is an analog layout generator using programmable routing with Pcells. The first work proposes a high-speed SAR ADC implemented in a 28nm CMOS process. The architecture employs a subrange ADC to increase conversion speed, settling time relief techniques to gain more conversion time, and a detect-and-skip algorithm to improve linearity and reduce switching energy. The high-speed SAR ADC achieves an ENOB of 8.53 bits, an SFDR of 56.2 dB, and an SNDR of 53.1 dB at an Fs of 200MS/s and a Fin of 10MHz, with a power consumption of 1.8 mW. At an Fs of 300 MS/s and a Nyquist input frequency of 150MHz, it achieves an ENOB of 7.41 bits, an SFDR of 54.77 dB, and an SNDR of 46.35 dB, with a power consumption of 2.5 mW. The second work introduces an analog layout generator using programmable routing with Pcells for analog layout generation. The optimization involves three steps, including MOSFET creation, guard ring creation, and symmetry techniques. These optimizations enable the analog layout generator to produce layouts similar to custom-made layouts and have been implemented in a reference voltage buffer circuit using a 40nm process. The areas of the analog layout generator and the custom-made layout are 150.3 μm2 and 144.7 μm2.