請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91387
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹 | zh_TW |
dc.contributor.advisor | Hsin-Shu Chen | en |
dc.contributor.author | 蔡旻修 | zh_TW |
dc.contributor.author | Min-Shiou Tsai | en |
dc.date.accessioned | 2024-01-26T16:16:48Z | - |
dc.date.available | 2024-01-27 | - |
dc.date.copyright | 2024-01-26 | - |
dc.date.issued | 2024 | - |
dc.date.submitted | 2024-01-15 | - |
dc.identifier.citation | [1] G. Huang et al., "A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications," IEEE Journal of Solid-State Circuits, vol. 47, no. 11, pp. 2783-2795, Nov. 2012.
[2] S. Hsieh, et al., "A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC," 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. [3] Y. Chung et al., "A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 1, pp. 10-18, Jan. 2015. [4] M. Liu et al., "A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free "Swap To Reset," " in IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 2979-2990, Nov. 2017. [5] H. Tai et al., "A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 196-197. [6] Y. Hu et al., "An 89.55dB-SFDR 179.6dB-FoMs 12-bit 1MS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration, " 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), Tainan, 2018, pp. 253-256. [7] W. Liu et al., "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration," in IEEE Journal of Solid-State Circuits, vol. 46, no. 11, pp. 2661-2672, Nov. 2011. [8] Yuan Zhou et al., "A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration," 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2. [9] W. Tseng et al., "A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters," IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2222-2231, Oct. 2016. [10] D. Chang et al., "Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 322-332, Feb. 2017. [11] C. C. Lee, et al., "A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS," 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C62-C63. [12] V. Hariprasath et al., "Merged Capacitor Switching Based SAR ADC with Highest Switching Energy-Efficiency," Electron. Lett., vol. 46, pp. 620-621, Apr. 2010. [13] Y.-Z Lin et al., "An 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with Fast Reference Charge Neutralization and Background Timing-Skew Calibration in 16-nm CMOS," in Proc. IEEE Symp. VLSI Circuits, pp.C204-C205, Jun. 2016. [14] M. Liu et al., "A 106 nW 10 b 80 kS/s SAR ADC With Duty-Cycled Reference Generation in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2435-2445, Oct 2016. [15] Y. S. Hu et al., "A 0.6 V 6.4 fJ/conversion-step 10-bit 150 MS/s Subranging SAR ADC in 40 nm CMOS," IEEE Asian Solid-State Circuits Conference, pp. 81-84, 2014. [16] F. Kuttner, "A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS," in IEEE ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2002. [17] C.-C. Liu et al., ”A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010 [18] H. Kang, H. Hong, W. Kim, and S. Ryu, "A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme," IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2584-2594, 2018 [19] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s," in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [20] B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier," IEEE Journal of Solid-State Circuits, pp. 1148-1158, July. 2004. [21] B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC", IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739- 747, Apr. 2007. [22] C. Liu, et al., "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [23] V. Hariprasath, et al., “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” IEEE Electronics Letters, vol. 46, no. 9, pp. 620-621, Apr. 2010. [24] Shuo-Wei Mike Chen and R. W. Brodersen, "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13/spl mu/m CMOS," in IEEE ISSCC Dig. Tech. Papers, pp. 2350-2359, Feb. 2006. [25] P. R. Surkanti, A. Garimella and P. M. Furth, "Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview," 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, India, 2018, pp. 232-237. [26] J. Rijmenants, J. B. Litsios, T. R. Schwarz, and M. G. R. Degrauwe, “ILAC: An automated layout tool for analog CMOS circuits,” IEEE J.Solid-State Circuits, vol. 24, no. 2, pp. 417–425, Apr. 1989. [27] J. D. Bruce, H. W. Li, M. J. Dallabetta, and R. J. Baker, "Analog layout using ALAS!" IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 271–274, Feb. 1996. [28] Carsten Wulff et al., "Compiled 9-bit 20-MS 3.5-fJ-conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers," in IEEE Journal of Solid-State Circuits. [29] Hui-Ya Chen. (2021). A Hybrid Reference Buffer Circuit for an ADC and Optimized Programmable Routing in Analog Layout. Master Thesis, Mixed-Signal IC Lab, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei City. [30] H. Huang, H. Xu, B. Elies and Y. Chiu, "A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation," IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3235-3247, 2017. [31] Q. Yu et al., "A 9.08 ENOB 10 b 400 MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40 nm CMOS," IEEE 47th European Solid State Circuits Conference (ESSCIRC), pp. 391-394, 2021. [32] Liu, C. -Cheng, C. -H. Kuo and Y. -Z. Lin, "A 10 bit 320 MS/s low-cost SAR ADC for IEEE 802.11 ac applications in 20 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 50, no. 11, pp. 2645-2654, 2015. [33] K. -I. Cho et al., "A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling," IEEE Asian Solid-State Circuits Conference (A-SSCC), 2020. [34] W. C. Black, Jr., and D. A. Hodges, “Time interleaved converter arrays,” IEEE J.Solid-State Circuits, vol. SC-15, no. 6, pp. 1022–1029, Dec. 1980. [35] C.-C. Liu, et al., “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Papers, Feb. 2010, pp. 386–387. [36] S.-H. Cho et al., “A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1881–1892, Aug. 2011. [37] H.-Y. Tai, H.-W. Chen and H.-S. Chen, “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” in IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 92–93. [38] Y. -J. Roh, D. -J. Chang and S. -T. Ryu, "A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 2833-2837, Dec. 2020. [39] J. Guerber, H. Venkatram, M. Gande, A. Waters, and U.-K. Moon, “A 10-b Ternary SAR ADC With Quantization Time Information Utilization,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2604–2613, Nov. 2012. [40] H.-Y. Tai, P.-Y. Tsai, C.-H. Tsai, and H.-S. Chen, “A 0.004mm2 Single-Channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS,” Asian Solid-State Circuits Conf., pp. 277-280, Nov. 2013. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91387 | - |
dc.description.abstract | 本論文分別有兩個題目,第一個是高速連續漸進式類比至數位轉換器,第二個是參數化單元之可程式化繞線用於類比佈局產生器。
本論文第一個題目提出一個高速連續漸進式類比至數位轉換器,實現於二十八奈米製程,架構上採用次區間類比至數位轉換器,來提高轉換速度,採用安定時間緩解技巧來獲得更多轉換時間,也採用了偵測與迴避演算法來改善線性度及降低切換功耗。 此高速連續漸進式類比至數位轉換器在每秒二億取樣頻率、一千萬輸入頻率時,可以達到八點五三的有效位元,無雜散訊號動態範圍為五十六點二分貝,訊號對雜訊失真比為五十三點一分貝,功耗為一點八毫瓦。而在每秒三億取樣頻率、奈奎斯特一點五億輸入頻率時,可以達到七點四一的有效位元,無雜散訊號動態範圍為五十四點七七分貝,訊號對雜訊失真比為四十六點三五分貝,功耗為二點五毫瓦。 本論文第二個題目提出使用參數化單元之可程式化繞線用於類比佈局產生器,優化包括三個步驟,電晶體創建、保護環創建、對稱技巧,這些優化使得類比佈局生成器能夠生成與自定義佈局相似的佈局,並實現於一個採用四十奈米製程的參考電壓緩衝電路,類比佈局生成器與自定義佈局的面積分別為一百五十點三微米平方及一百四十四點七微米平方。 | zh_TW |
dc.description.abstract | This thesis consists of two works: the first one is a high-speed SAR ADC, and the second one is an analog layout generator using programmable routing with Pcells.
The first work proposes a high-speed SAR ADC implemented in a 28nm CMOS process. The architecture employs a subrange ADC to increase conversion speed, settling time relief techniques to gain more conversion time, and a detect-and-skip algorithm to improve linearity and reduce switching energy. The high-speed SAR ADC achieves an ENOB of 8.53 bits, an SFDR of 56.2 dB, and an SNDR of 53.1 dB at an Fs of 200MS/s and a Fin of 10MHz, with a power consumption of 1.8 mW. At an Fs of 300 MS/s and a Nyquist input frequency of 150MHz, it achieves an ENOB of 7.41 bits, an SFDR of 54.77 dB, and an SNDR of 46.35 dB, with a power consumption of 2.5 mW. The second work introduces an analog layout generator using programmable routing with Pcells for analog layout generation. The optimization involves three steps, including MOSFET creation, guard ring creation, and symmetry techniques. These optimizations enable the analog layout generator to produce layouts similar to custom-made layouts and have been implemented in a reference voltage buffer circuit using a 40nm process. The areas of the analog layout generator and the custom-made layout are 150.3 μm2 and 144.7 μm2. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-01-26T16:16:48Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2024-01-26T16:16:48Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | CONTENTS
論文口試委員審定書 i 致謝 ii 摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES ix LIST OF TABLES xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of An ADC and An Analog Layout Generator 4 2.1 Introduction 4 2.2 Analog-to-Digital Converter 4 2.2.1 Static Performance 4 2.2.1.1 Offset Error 4 2.2.1.2 Gain Error 5 2.2.1.3 Differential and Integral Nonlinearity (DNL and INL) 6 2.2.2 Dynamic Performance 7 2.2.2.1 Signal-to-Noise Ratio (SNR) 7 2.2.2.2 Total Harmonic Distortion (THD) 8 2.2.2.3 Spurious-Free Dynamic Range (SFDR) 8 2.2.2.4 Signal-to-Noise and Distortion Ratio (SNDR) 8 2.2.2.5 Effective Number of Bits (ENOB) 9 2.2.2.6 Figure of Merit (FoM) 9 2.2.3 Architectures 10 2.2.3.1 Pipeline 10 2.2.3.2 Successive-Approximation-Register(SAR) 11 2.2.3.3 Two-Step and Sub-Ranging 12 2.2.3.4 Time-Interleaved 13 2.2.4 Energy-Efficient Capacitor Switching Algorithm 15 2.2.4.1 Split-capacitor Switching 15 2.2.4.2 Monotonic Switching 16 2.2.4.3 Vcm-Based Switching 17 2.2.5 Redundancy 19 2.3 Analog Layout Generator 22 2.3.1 Compilation 22 2.3.2 MOSFET Creation 24 2.3.3 Placement 26 2.3.4 Routing 27 2.3.4.1 Route-type 28 2.3.4.2 Options 30 Chapter 3 High-Speed Subrange SAR ADC 33 3.1 Introduction 33 3.2 Proposed Architecture 33 3.2.1 Coarse ADC 34 3.2.2 Settling Time Relief Technique 37 3.2.3 Detect-and-Skip (DAS) Algorithm 38 3.2.4 Error Correction Technique 40 3.3 Circuit Implementation 42 3.3.1 Bootstrapped Circuit 42 3.3.2 Comparator Circuit 45 3.3.2.1 Speed 46 3.3.2.2 Noise 48 3.3.2.3 Offset 49 3.3.3 C-DAC 50 3.3.4 SAR Digital Logic 51 3.3.5 Input Buffer 53 3.3.6 Reference Buffer 54 3.4 Simulation 56 3.4.1 Post-Layout Simulation 56 3.4.2 Corner Simulation 57 3.5 Measurement 58 3.5.1 Measurement Setup 58 3.5.1.1 Chip Layout 59 3.5.1.2 PCB Layout 60 3.5.2 Measurement Result 62 3.5.2.1 Static Performance 62 3.5.2.2 Dynamic Performance 62 3.5.2.3 Power Consumption 65 3.5.2.4 Measurement Discussion 65 3.5.2.5 Summary of ADC 67 Chapter 4 Analog Layout Generator using Programmable Routing with Pcells (PRP) 68 4.1 Introduction 68 4.2 MOSFET Creation 69 4.2.1 GDSII Format 70 4.2.2 MOS Creation with Pcells 71 4.3 Guard Ring Creation and Placement 76 4.3.1 Guard Ring for Instance 79 4.3.2 Guard Ring for Multiple Instances 83 4.3.3 Shared Guard Ring for Instance 85 4.3.4 Summary of Guard Ring Creation 89 4.4 Symmetry 90 4.5 Summary of PRP 93 4.5.1 PRP Flowchart 93 4.5.2 Case Implementation 95 4.5.3 Comparison 96 4.5.4 Design time 97 Chapter 5 Conclusions 98 5.1 Conclusion 98 5.2 Future Work 99 Bibliography 100 | - |
dc.language.iso | en | - |
dc.title | 一個高速連續漸進式類比至數位轉換器與類比佈局產生器使用參數化單元之可程式化繞線 | zh_TW |
dc.title | A High-Speed SAR ADC and An Analog Layout Generator using Programmable Routing with Pcells | en |
dc.type | Thesis | - |
dc.date.schoolyear | 112-1 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 胡耀升;蔡坤諭 | zh_TW |
dc.contributor.oralexamcommittee | Yao-Sheng Hu;Kuen-Yu Tsai | en |
dc.subject.keyword | 類比至數位轉換器,連續漸進式,次區間,可程式化繞線, | zh_TW |
dc.subject.keyword | Analog-to-digital converters (ADC),Successive-approximation register (SAR),Subrange,Programmable Routing, | en |
dc.relation.page | 104 | - |
dc.identifier.doi | 10.6342/NTU202400097 | - |
dc.rights.note | 未授權 | - |
dc.date.accepted | 2024-01-16 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-112-1.pdf 目前未授權公開取用 | 4.8 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。