一種具有更寬擷取範圍相位偵測器的次採樣鎖相迴路

Abstract

在當今的車用電子和自動駕駛應用中，電路不僅需要滿足高速、低延遲的傳輸特性，低噪聲和高環境耐受特性也是重要指標。訊號在傳輸時需要可信的時脈支持，因此鎖相迴路被使用以來產生時脈信號。比較電荷泵鎖相迴路和次採樣鎖相迴路，次採樣鎖相迴路具有更好的抖動性能。然而，由於次採樣相位偵測器的捕獲範圍有限，次採樣鎖相迴路存在擷取能力問題。為了改善次採樣鎖相迴路的擷取能力問題，本論文提出了 “一種具有更寬擷取範圍相位偵測器的次採樣鎖相迴路”，以滿足車用電子高環境耐受性的需求。 晶片使用技術為 TSMC 28nm 製程。在量測結果中，提出之次採樣鎖相迴路在 0.9V 供電源消耗 18.91mW，晶片之核心電路總面積為 0.114 × 0.320 mm2。提出之次採樣鎖相迴路在 14MHz 參考輸入頻率 5.6GHz 鎖相迴路輸出頻率下，其 FoM 為-210.2。次取樣鎖相迴路最大允許壓控震盪器抖動性能在提出之次採樣鎖相迴路架構亦比傳統次採樣鎖相迴路好至少10%。

Nowadays, in automotive electronics and autonomous driving applications, chip circuits not only need to meet high-speed, low-latency transmission characteristics, and low noise and high environmental tolerance characteristics are also important indicators. Signal transmission needs to be supported by a reliable clock signal, and a phase-locked loop (PLL) is used to generate the clock signal. Comparing the charge-pump phase-locked loop (CPPLL) and the sub-sampling phase-locked loop (SSPLL), SSPLL has better jitter performance. However, there is a capture ability issue in SSPLL due to the limited capture range of the sub-sampling phase detector (SSPD). In order to improve the capture ability problem of SSPLL, “a SSPLL with a wider capture range phase detector” is proposed in this thesis, which can be used to meet the high environmental tolerance requirements of automotive electronics. The chip is fabricated in the TSMC 28nm technology. In the measurement result, the proposed SSPLL consumes 18.91mW from a 0.9V supply and occupies an active area of 0.114 × 0.320 mm2. The FoM of SSPLL (F oMSSPLL) is -210.2 with 14MHz reference input frequency and 5.6GHz SSPLL output frequency. SSPLL maximum allowable VCO jitter performance of the proposed SSPLL is better than that of the traditional SSPLL by at least 10%.