具有管線式循序漸進量化器加速之混合式連續時間三角積分類比數位轉換器分析與設計

Abstract

隨著時間的演進，高速的應用如雨後春筍般出現，高速、高解析、低功耗的類比數位轉換器逐漸受到重視。主流的架構為天生具有抗混疊功能的連續時間三角積分調變器。我們知道，影響三角積分調變器的效能有超取樣率、雜訊轉移函數階數、量化器位元數以及取樣頻率。當三角積分調變器的頻寬需求越來越高，超取樣率會受到限制。在較低超取樣率的條件下要達到較好的訊號雜訊失真比需要較高階數的雜訊轉移函數或者較多位元的量化器。高階數的雜訊轉移函數會使系統對元件的變異敏感且較容易達到不穩定的狀態，多位元的量化器之速度、量化時間產生的額外延遲、時脈抖動對回授到迴路濾波器的影響皆會影響三角積分調變器的性能。

本論文提出了一種超取樣率為六且具有量化器加速之混合管線式循序漸進與連續三角積分類比數位轉換器，調變器是採用聯電二十二奈米互補式金屬氧化物半導體製程實現。在取樣頻率為十億零五千萬赫茲下得到 44.66 分貝的訊號雜訊失真比，功耗為 93.35 毫瓦。

High-speed applications of analog-to-digital converters (ADCs) are increasing these years, especially on high-speed, high-resolution and low-power ones. The continuous-time delta-sigma modulator (CT-DSM) with inherent anti-aliasing feature is a commonly used structure. We know that the oversampling ratio (OSR), noise transfer function (NTF), quantizer bits and sampling rate are the main variables for a CT-DSM. To achieve high bandwidth, the OSR is limited. Under low OSR, we need a high-order NTF or high-resolution quantizer to realize high signal-to-noise-and-distortion ratio (SNDR). However, high-order NTF is vulnerable to device variation and would get unstable easily. On the other hand, high-resolution quantizer would degrade the DSM performance due to excess delay or clock jitter.

This thesis proposes a hybrid pipelined-SAR/CT-DSM ADC with quantizer acceleration technique at OSR of 6. The modulator is fabricated with UMC 22 nm CMOS technology. We obtain a 44.66 dB SNDR at sampling rate of 1.05 GHz with 93.35 mW power consumption.