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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89869完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 呂曜銘 | zh_TW |
| dc.contributor.author | Yao-Ming Lu | en |
| dc.date.accessioned | 2023-09-22T16:28:19Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-09-22 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-11 | - |
| dc.identifier.citation | [1] S. Pavan, R. Schreier, and G. C. Temes, Understanding delta-sigma data converters. John Wiley & Sons, 2017.
[2] B. Ginsburg and A. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” in 2005 IEEE International Symposium on Circuits and Systems, vol. 1, pp. 184–187, May 2005. [3] O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, and U.-K. Moon, “Design of a 79 dB 80 Mhz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 719–730, April 2010. [4] C.-K. Hsu, X. Tang, J. Liu, R. Xu, W. Zhao, A. Mukherjee, T. R. Andeen, and N. Sun, “A 77.1-dB-SNDR 6.25-MHz-BW pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping,” IEEE Journal of Solid-State Circuits, vol. 56, pp. 739–749, March 2021. [5] M. Ortmanns, F. Gerfers, and Y. Manoli, “A continuous-time Sigma Delta Modulator with reduced sensitivity to clock jitter through SCR feedback,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, pp. 875–884, May 2005. [6] M. Ortmanns, F. Gerfers, and Y. Manoli, “Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, pp. 1088–1099, June 2004. [7] F. Gerfers, M. Ortmanns, and Y. Manoli, “A 1.5V 12bit power-efficient continuous-time third-order Σ∆ modulator,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 1343–1352, August 2003. [8] S. Yan and E. Sánchez-Sinencio, “A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth,” IEEE Journal of SolidState Circuits, vol. 39, pp. 75–86, January 2004. [9] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Romani, A. Melodia, and V. Melini, “A 14b 20mW 640MHz CMOS CT Delta Sigma ADC with 20MHz Signal Bandwidth and 12b ENOB,” in 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, pp. 131–140, February 2006. [10] Y.-H. Wu, “Design and Analysis of a Hybrid Continuous-time Delta-Sigma/Pipelined-SAR ADC,” master’s thesis, National Taiwan University, Taipei, Taiwan, January 2023. [11] T. Jiang, W. Liu, F. Y. Zhong, C. Zhong, and P. Y. Chiang, “Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS,” in IEEE Custom Integrated Circuits Conference 2010, pp. 1–4, September 2010. [12] H.-H. Chang, T.-C. Lin, and T.-C. Lee, “A Single-Channel 1GS/s 7.48 ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, pp. 2021–2025, April 2022. [13] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 731–740, April 2010. [14] B. Razavi, “The bootstrapped switch [a circuit for all seasons],” IEEE Solid-State Circuits Magazine, vol. 7, pp. 12–15, June 2015. [15] J. Lin, M. Miyahara, and A. Matsuzawa, “A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique,” in 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp. 21–24, May 2011. [16] M. Zhang, Q. Liu, and X. Fan, “Gain-boosted dynamic amplifier for pipelined-SAR ADCs,” Electronics Letters, vol. 53, pp. 708–709, May 2017. [17] D.Y. Yoon, H.S. Lee, J. Gealow, “Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators,” in 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 562–565, August 2013. [18] B. Murmann, “ADC Performance Survey 19972023.” [Online]. Available: https://web.stanford.edu/~murmann/adcsurvey.html, 2023. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89869 | - |
| dc.description.abstract | 隨著時間的演進，高速的應用如雨後春筍般出現，高速、高解析、低功耗的類比數位轉換器逐漸受到重視。主流的架構為天生具有抗混疊功能的連續時間三角積分調變器。我們知道，影響三角積分調變器的效能有超取樣率、雜訊轉移函數階數、量化器位元數以及取樣頻率。當三角積分調變器的頻寬需求越來越高，超取樣率會受到限制。在較低超取樣率的條件下要達到較好的訊號雜訊失真比需要較高階數的雜訊轉移函數或者較多位元的量化器。高階數的雜訊轉移函數會使系統對元件的變異敏感且較容易達到不穩定的狀態，多位元的量化器之速度、量化時間產生的額外延遲、時脈抖動對回授到迴路濾波器的影響皆會影響三角積分調變器的性能。
本論文提出了一種超取樣率為六且具有量化器加速之混合管線式循序漸進與連續三角積分類比數位轉換器，調變器是採用聯電二十二奈米互補式金屬氧化物半導體製程實現。在取樣頻率為十億零五千萬赫茲下得到 44.66 分貝的訊號雜訊失真比，功耗為 93.35 毫瓦。 | zh_TW |
| dc.description.abstract | High-speed applications of analog-to-digital converters (ADCs) are increasing these years, especially on high-speed, high-resolution and low-power ones. The continuous-time delta-sigma modulator (CT-DSM) with inherent anti-aliasing feature is a commonly used structure. We know that the oversampling ratio (OSR), noise transfer function (NTF), quantizer bits and sampling rate are the main variables for a CT-DSM. To achieve high bandwidth, the OSR is limited. Under low OSR, we need a high-order NTF or high-resolution quantizer to realize high signal-to-noise-and-distortion ratio (SNDR). However, high-order NTF is vulnerable to device variation and would get unstable easily. On the other hand, high-resolution quantizer would degrade the DSM performance due to excess delay or clock jitter.
This thesis proposes a hybrid pipelined-SAR/CT-DSM ADC with quantizer acceleration technique at OSR of 6. The modulator is fabricated with UMC 22 nm CMOS technology. We obtain a 44.66 dB SNDR at sampling rate of 1.05 GHz with 93.35 mW power consumption. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-09-22T16:28:19Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-09-22T16:28:19Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Contents
誌謝 iii 摘要 v Abstract vi 1 Introduction 1 1.1 Motivation and Research Goals . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Fundamental 4 2.1 Introduction of analogtodigital converters . . . . . . . . . . . . . . . . 4 2.2 ADC Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Delta Sigma Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 Introduction of DeltaSigma ADC system . . . . . . . . . . . . . 13 2.3.2 AntiAliasing Filter (AAF) . . . . . . . . . . . . . . . . . . . . . 14 2.3.3 CTDSM & DTDSM Introduction and Comparison . . . . . . . . 21 2.4 Successive Approximation Register (SAR) ADCs . . . . . . . . . . . . . 24 3 Proposed Architecture Analysis 27 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3 System NonIdealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.1 Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.2 Clock Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.3 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.4 Flicker Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.5 Operational Amplifier’s NonIdealities . . . . . . . . . . . . . . 32 3.3.6 Excess Loop Delay Compensation . . . . . . . . . . . . . . . . . 33 3.4 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.1 TwoStage PipelinedSAR ADC . . . . . . . . . . . . . . . . . . 37 3.4.2 Systematic Design of Loop Filter . . . . . . . . . . . . . . . . . 40 3.4.3 Proposed Architecture DTCT Transformation . . . . . . . . . . 41 3.4.4 Gain Error On Feedback Paths . . . . . . . . . . . . . . . . . . . 44 3.4.5 Gain Error On PreDynamic Amplifier . . . . . . . . . . . . . . 45 4 Simulation and Analysis of VCCS and DA Gain Error Shaping Technique 47 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 VCCS Gain Error and VCCS Gain Error Shaping . . . . . . . . . . . . . 47 4.3 Dynamic Amplifier Gain Error and Dynamic Amplifier Gain Error Shaping 51 4.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5 Circuit Implementation 59 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.2 TwoStage Pipelined SAR ADC . . . . . . . . . . . . . . . . . . . . . . 59 5.2.1 First Stage SAR ADC . . . . . . . . . . . . . . . . . . . . . . . 61 5.2.2 Second Stage SAR ADC . . . . . . . . . . . . . . . . . . . . . . 62 5.2.3 Parallel Conversion . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.4 Dynamic Amplifier’s Capacitor Array (DACA) and Pre Dynamic Amplifier Capacitor Array (PreDA CA) . . . . . . . . . . . . . 64 5.2.5 Dynamic Amplifier and PreDynamic Amplifier . . . . . . . . . 65 5.3 Current DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.4 VoltageControlled Current Source . . . . . . . . . . . . . . . . . . . . . 71 5.4.1 VoltageControlled Current Source’s Capacitor Array (VCCSCA) 73 5.5 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.6 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.7.1 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.7.2 Circuit Level Parameters . . . . . . . . . . . . . . . . . . . . . . 83 5.7.3 DACA’s Thermal Noise . . . . . . . . . . . . . . . . . . . . . . 83 5.7.4 VCCSCA’s Thermal Noise . . . . . . . . . . . . . . . . . . . . . 85 5.8 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.9 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6 Measurement Results 93 6.1 Chip Micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.2 Printed Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.1 PostProcessing . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.4 Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7 Conclusion 105 7.1 FigureofMerit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Bibliography 107 | - |
| dc.language.iso | en | - |
| dc.subject | 雜訊整形 | zh_TW |
| dc.subject | 增益誤差整形 | zh_TW |
| dc.subject | 三角積分調變器 | zh_TW |
| dc.subject | 管線式循序漸進類比數位轉換器 | zh_TW |
| dc.subject | 超取樣轉換器 | zh_TW |
| dc.subject | 迴授數位類比轉換器 | zh_TW |
| dc.subject | 迴路濾波器 | zh_TW |
| dc.subject | Delta-sigma modulation | en |
| dc.subject | loop filter | en |
| dc.subject | feedback DAC | en |
| dc.subject | oversampling converters | en |
| dc.subject | pipelined-SAR analog-to-digital converters | en |
| dc.subject | noise shaping | en |
| dc.subject | gain error shaping | en |
| dc.title | 具有管線式循序漸進量化器加速之混合式連續時間三角積分類比數位轉換器分析與設計 | zh_TW |
| dc.title | Design and Analysis of a Hybrid Continuous-time Delta-Sigma modulator/Pipelined-SAR ADC with Quantizer Acceleration Technique | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉深淵;陳筱青 | zh_TW |
| dc.contributor.oralexamcommittee | Shen-Iuan Liu;Hsiao-Chin Chen | en |
| dc.subject.keyword | 三角積分調變器,管線式循序漸進類比數位轉換器,超取樣轉換器,迴授數位類比轉換器,迴路濾波器,雜訊整形,增益誤差整形, | zh_TW |
| dc.subject.keyword | Delta-sigma modulation,pipelined-SAR analog-to-digital converters,oversampling converters,feedback DAC,loop filter,noise shaping,gain error shaping, | en |
| dc.relation.page | 109 | - |
| dc.identifier.doi | 10.6342/NTU202301859 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-08-12 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2028-08-01 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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