應用於高輸入電壓之壓電能量擷取系統的同步反轉和電荷提取介面電路

Abstract

物聯網和各種無線電設備的廣泛使用，意味著智能生態系統已經融進了我們的日常生活裡。然而，這些設備的供電仍是個值得注意的問題。 雖然使用一次性電池非常方便，但會帶來一些後果，包括電池定期更換和廢棄電池造成的環境污染。因其普遍性和在可取得的室內源中是最能提供高功率密度，環境振動成了最具前瞻性的替代方案。本論文利用所提出的AC-DC介面電路將從壓電收集器收集到的振動能量整流。 壓電收集器的目標是增加其輸出功率，而如今的先進製程其工作電壓是趨向更低。 擷取能量且不損壞介面電路，的確實是個挑戰。本論文提供在落實介面積體電路的過程中所遇到輸入電壓受局限的解決方案。 壓電能量擷取系統裡兩種常見介面電路, 同步切換電感式能量擷取介面電路(SSHI)和同步電荷擷取介面電路(SECE)的結合，又稱同步反相和電荷提取 (SICE)介面電路，可同時提供高功率增益和負載獨立性的雙重優點。一種基於SICE的介面電路， 可處理高於元件閘極-源極間VGS 的最大耐壓的輸入電壓被提出來。採用台積電 0.18 μm HV-CMOS 製程來達成，其元件的VGS 最大耐壓為 5 V。若使用傳統的壓電能量擷取介面電路，輸入電壓被限制不可超過 5 V，因此可擷取的能量被限制住。利用所提出的閘極電壓控制電路，所提出的介面電可允許 5 V 以上至VDS 最大耐壓（12 V）的輸入電壓且不至於發生擊穿。作為高電壓節點與控制電路間介面電路的新穎負電壓轉換器也被提出來。根據量測結果，在壓電電壓峰值為 8.8 V 時，可擷取到11.56 μW的輸出功率，相當於產生 45% 的功率增益，且還可同時顯現出其負載獨立性。

The widespread usage of the Internet of Things and various wireless electrical devices depicts the integration of smart ecosystems into our daily lives. However, powering these devices remains a significant issue. Although using disposable batteries is convenient, the consequences may engender additional problems, such as regular battery replacement and environmental pollution from discarded batteries. Due to its ubiquity and ability to provide high power density, ambient vibration is the most promising alternative among available indoor resources. This thesis proposed an AC-DC interface circuit to rectify the vibration energy captured by the piezoelectric harvester. Piezoelectric harvesters aim to increase output power, whereas the operating voltage of emerging technologies nowadays is going lower. Harnessing energy without damaging the interface circuit becomes a challenging matter. This thesis proposes a solution for input voltage limitations encountered upon implementing the integrated interface circuit. A combination of two common interface circuits in piezoelectric energy harvesting, Synchronized Switch Harvesting on Inductor (SSHI) and Synchronous Electric Charge Extraction (SECE), known as the Synchronous Inversion and Charge Extraction (SICE) interface circuit, can simultaneously provide the benefits of high power gain and loading-independent property. A SICE-based interface circuit for handling input voltage higher than the maximum VGS voltage rating is proposed. It is implemented with TSMC 0.18 μm HV-CMOS process, where its devices have a VGS voltage rating of 5 V. With conventional harvesting schemes, the input voltage is restricted from exceeding 5 V, thus limiting the harvestable energy. Using the proposed gate voltage controller, the proposed interface circuit can handle input voltages beyond 5 V up to VDS voltage rating (12 V) without breakdown. Also, a novel mechanism for a negative voltage converter is proposed as an interface between the high voltage nodes and control circuits. It can extract an output power of up to 11.56 μW when the piezoelectric voltage peak is 8.8 V, resulting in a power gain of 45% as per measurement results and being load-independent simultaneously.