Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8859
Title: | JPEG-LS編碼器之平行管線化架構實作 A Parallel Pipelined Implementation for JPEG-LS Encoders |
Authors: | Chia-Hsiang Lin 林家興 |
Advisor: | 王勝德(Sheng-De Wang) |
Keyword: | JPEG-LS,平行化,管線化,SOPC,FPGA, JPEG-LS,Parallel,Pipeline,SOPC,FPGA, |
Publication Year : | 2009 |
Degree: | 碩士 |
Abstract: | 隨著醫學電子的蓬勃發展,在醫學影像的處理上勢必越來越受重視,而且畫素也會隨著科技的進步來不斷的提升,造成圖片尺寸越來越大,適當運用無失真壓縮技術不但能方便儲存管理圖片,也可以使用在可攜式的電子醫學儀器上,讓使用者方便儲存以及讀取圖片。
JPEG-LS是國際標準的壓縮技術之一,在本論文中我們使用Verilog HDL來實作JPEG-LS編碼器,最後在FPGA (Field Programmable Gate Array )上面做驗證,在此我們提出在不需要增加額外的硬體電路時,利用平行化、管線化、模組化的特點,改良其電路架構後,就可以加速JPEG-LS的編碼電路約13~15%的時間。 JPEG-LS is an international standard for lossless and near-lossless image compression. In this paper, a hardware implementation using Verilog HDL is proposed for a JPEG-LS encoder. The hardware design for the JPEG-LS encoder is tested in a Field Programmable Gate Array (FPGA). JPEG-LS Encoders have two main data compression modules, Regular mode and Run mode. We separate some modules such as Line Buffer, Regular mode, Run mode, Golomb Encoder, and update parameters from each other. We also share the module parameters to reduce the gate number. The architecture developed is a pipelined parallel design, which can speed up 13~15% the JPEG-LS encoder compression performance. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8859 |
Fulltext Rights: | 同意授權(全球公開) |
Appears in Collections: | 電機工程學系 |
Files in This Item:
File | Size | Format | |
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ntu-98-1.pdf | 1.62 MB | Adobe PDF | View/Open |
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