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???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
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dc.contributor.advisor | 王勝德(Sheng-De Wang) | |
dc.contributor.author | Chia-Hsiang Lin | en |
dc.contributor.author | 林家興 | zh_TW |
dc.date.accessioned | 2021-05-20T20:02:45Z | - |
dc.date.available | 2011-08-20 | |
dc.date.available | 2021-05-20T20:02:45Z | - |
dc.date.copyright | 2009-08-20 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-08-19 | |
dc.identifier.citation | [1] JPEG/JBIG, FCD 14495, Lossless and near-lossless coding of continuous tone still images, 2000.http://www.jpeg.org/public/fcd14495p.pdf
[2] Xiaolin Chen, Nishan Canagarajah, Jose L. Nunez-Yanez “Hardware Architecture for Lossless Image Compression Based on Context-based Modeling and Arithmetic Coding”, SOC Conference, 2007 IEEE International Volume, Issue, 26-29, Sept 2007, pp.251 - 254 [3] Shantanu D. Rane and Guillermo Sapiro, ”Evaluation of JPEG-LS, the New Lossless and Controlled-Lossy Still Image Compression Standard,for Compression of High-Resolution Elevation Data”, IEEE Trans, Vol.39, issue10, OCTOBER 2001, pp.2298-2306 [4] Jiang,J, Grecos C, ”A low cost design of rate controlled JPEG-LS near lossless image Compression”, Image & Vision Computing Journal, ELSEVIER, Vol 19, No 3, Feb.2001, pp.153-164 [5] Markos Papadonikolakis, Vasilleios Pantazis and Athanasios P. Kakarountas “Efficient High-Performance ASIC Implementation of JPEG-LS Encoder”, Design Automation & Test in Europe Conference & Exhibition, April 2007, pp. 1-6 [6] Xiang Xie, GuoLin Li and ZhiHua Wang, “A Near-lossless Image Compression Algorithm Suitable for Hardware Design in Wireless Endoscopy System”, Department of Electronic Engineering, Tsinghua University, Beijing, P. R. China, 100084, ASICON 2005. 6th International Conference On ASIC, Volume 1, 24-27 Oct. 2005 pp. 37 -40 [7] S. W. Golomb, “Run-length encodings” IEEE Trans, Inform.Theory, vol. IT-12, July 1966. pp. 399-401 [8] M Ferretti, M. Boffadossi, “A Parallel Pipelined Implementation for JPEG-LS”, International Conference on Pattern Recognition (ICPR’04), vol.1, pp. 769-772. [9] A. Savakis and M. Pioriun, “Benchmarking and Hardware Implementation of JPEG-LS”, International Conference on Image Processing Proceedings(ICIP’02) Vol. 2 Sep.2002, pp.949-952. [10] S.Hauck, ” The role of FPGAs in Reprogrammable Systems” Proceedings of The IEEE, VOL. 86, NO. 4 Apr.1998, pp.615-639 [11] M. Klimesh, V. Stanton, “Hardware Implementation of a Lossless Image Compression Algorithm Using a Field Programmable Gate Array, ” NASA JPL TMO 2001, Progress Report 42-144 [12] PPM Format Specification, http://netpbm.sourceforge.net/doc/ppm.html [13] Clunie, D.A. “Lossless compression of grayscale medical images: effectiveness of traditional and state of the art approaches.” Proc. SPIE Medical Imaging, 2000. [14] http://www.altera.com/ [15] Verilog數位電路設計, 鄭羽伸 編著 [16] Verilog硬體描述語言數位電路, 鄭信源 編著 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8859 | - |
dc.description.abstract | 隨著醫學電子的蓬勃發展,在醫學影像的處理上勢必越來越受重視,而且畫素也會隨著科技的進步來不斷的提升,造成圖片尺寸越來越大,適當運用無失真壓縮技術不但能方便儲存管理圖片,也可以使用在可攜式的電子醫學儀器上,讓使用者方便儲存以及讀取圖片。
JPEG-LS是國際標準的壓縮技術之一,在本論文中我們使用Verilog HDL來實作JPEG-LS編碼器,最後在FPGA (Field Programmable Gate Array )上面做驗證,在此我們提出在不需要增加額外的硬體電路時,利用平行化、管線化、模組化的特點,改良其電路架構後,就可以加速JPEG-LS的編碼電路約13~15%的時間。 | zh_TW |
dc.description.abstract | JPEG-LS is an international standard for lossless and near-lossless image compression. In this paper, a hardware implementation using Verilog HDL is proposed for a JPEG-LS encoder. The hardware design for the JPEG-LS encoder is tested in a Field Programmable Gate Array (FPGA).
JPEG-LS Encoders have two main data compression modules, Regular mode and Run mode. We separate some modules such as Line Buffer, Regular mode, Run mode, Golomb Encoder, and update parameters from each other. We also share the module parameters to reduce the gate number. The architecture developed is a pipelined parallel design, which can speed up 13~15% the JPEG-LS encoder compression performance. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T20:02:45Z (GMT). No. of bitstreams: 1 ntu-98-P95921008-1.pdf: 1663885 bytes, checksum: 0eeb68f481d782e7d3b728562c9c2594 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 目錄
第一章 緒論 1 1.1 研究動機 1 1.2 研究目標與貢獻 3 1.3 章節概述 5 第二章 JPEG-LS 編碼演算法 6 2.1編碼原理 6 2.2 壓縮步驟 7 第三章 JPEG-LS硬體壓縮電路之架構分析 15 3.1 PPM(Portable Pixel Map)檔案格式介紹 15 3.2 初始化硬體電路 18 3.3 輸入行緩衝器(Line Buffer) 19 3.4預測及修正值電路架構 20 3.5原始硬體架構 21 3.6改良的硬體架構 22 第四章 系統實作 24 4.1 電路模擬 24 4.2 使用ModelSim Library 25 4.3 Altera Quartus II 26 4.4 RTL 設計流程 27 4.5 RTL 編碼技巧 28 第五章 實驗結果 32 5.1 合成結果 32 5.2 測試資訊 35 5.3 效能估算 36 第六章 結論與未來工作 38 6.1結論 38 6.2未來工作 38 參考文獻 39 附錄A. 41 | |
dc.language.iso | zh-TW | |
dc.title | JPEG-LS編碼器之平行管線化架構實作 | zh_TW |
dc.title | A Parallel Pipelined Implementation for JPEG-LS Encoders | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 王凡(Farn Wang),洪士灝(Shih-Hao Hung) | |
dc.subject.keyword | JPEG-LS,平行化,管線化,SOPC,FPGA, | zh_TW |
dc.subject.keyword | JPEG-LS,Parallel,Pipeline,SOPC,FPGA, | en |
dc.relation.page | 46 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2009-08-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
Appears in Collections: | 電機工程學系 |
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File | Size | Format | |
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ntu-98-1.pdf | 1.62 MB | Adobe PDF | View/Open |
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