低功耗三角積分時間至數位轉換器

Abstract

此論文中闡述了低功耗的三角積分時間至數位轉換器的設計技巧，以時間暫存器來傳遞時域的量化誤差來達到高解析度的時間至數位轉換器。利用90-nm CMOS製程，所提出的一階三角積分時間至數位轉換器，操作在0.3伏特的情況下，晶片功耗為1.5微瓦，並且在50k赫茲的頻寬內有效位元數(ENOB)為10.9位元。此外，進一步利用相同的設計技巧實現二階的三角積分時間至數位轉換器，並以此時間至數位轉換器應用至電容式感測器介面電路，操作在0.6伏特的情況下，晶片功耗為11微瓦，此電容式感測器介面電路輸入電容範圍為0~5皮法拉，並在2k赫茲的頻寬內效位元數(ENOB)為9.8位元。

The thesis presents low power design techniques for delta-sigma time-to-digital (TDC) converters. By using time register to transfer the time-domain quantization error, the resolution of the TDC can be improved due to noise-shaping of the quantization error. Fabricated in 90-nm CMOS, the first-order delta-sigma TDC consumes a current of 5 uA from a 0.3-V supply. The circuit demonstrates an equivalent number of bits (ENOB) of 10.9 bits in 50 kHz signal bandwidth. Moreover, a capacitance-to-digital (CDC) converter with a second-order delta-sigma TDC is also presented. Consuming 18.4 uA from a 0.6-V supply, the second-order CDC achieves an ENOB of 9.8 bits in 2 kHz signal bandwidth with an input capacitance range of 5 pF.