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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂良鴻 | |
| dc.contributor.author | Chih-Kai Chang | en |
| dc.contributor.author | 張智凱 | zh_TW |
| dc.date.accessioned | 2021-05-19T17:58:29Z | - |
| dc.date.available | 2021-08-24 | |
| dc.date.available | 2021-05-19T17:58:29Z | - |
| dc.date.copyright | 2016-08-24 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-08-04 | |
| dc.identifier.citation | [1] P. Dudek, S. Szczepanski and J. V. Hatfield, 'A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line', IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, 2000.
[2] J. Yu , F. F. Dai and R. C. Jaeger, 'A 12 bit Vernier ring time-to-digital converter in 0.13 um digital CMOS technology', IEEE J. Solid-State Circuits, vol. 45, pp. 830-842, 2010. [3] M. Lee and A. A. Abidi, 'A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue', IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769-777, 2008. [4] A. Mäntyniemi, T. Rahkonen and J. Kostamovaara, 'A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method', IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3067-3078, 2009. [5] J.-S. Kim, Y.-H. Seo, Y. Suh, H.-J. Park and J.-Y. Sim, 'A 300-ms/s, 1.76-ps-resolution, 10-b asynchronous pipelined time-to-digital converter with on-chip digital background calibration in 0.13 um CMOS', IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 516-526, 2013. [6] S.-J. Kim, T. Kim, and H. Park, “A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology”, in VLSI Circuits Dig. Tech. Papers, Jun. 2014. [7] S.-J. Kim, W. Kim, M. Song, J. Kim, T. Kim, and H. Park, “A 0.6 V 1.17 ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14 nm FinFET technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 1–3. [8] M. Z. Straayer and M. H. Perrott, 'A multi-path gated ring oscillator TDC with first-order noise shaping', IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1089-1098, 2009. [9] A. Elshazly, S. Rao, B. Young and P. K. Hanumolu, 'A noise-shaping time-to-digital converter using switched-ring oscillators—Analysis, design, and measurement techniques', IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1184-1197, 2014. [10] Y. Cao, W. D. Cock, M. Steyaert and P. Leroux, '1-1-1 MASH ΔΣ time-to-digital converters with 6 ps resolution and third-order noise-shaping', IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2093-2106, 2012. [11] W. Yu, K. Kim and S. Cho, 'A 0.22 ps rms integrated noise 15 MHz bandwidth fourth-order ΔΣ time-to-digital converter using time-domain error-feedback filter', IEEE J. Solid-State Circuits, vol. 50, no. 5, pp. 1251-1262, 2015. [12] K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, “Managing sub-threshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS),” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 859–867, Apr.2006. [13] W. Yu, 'A 148 fsrms integrated noise 4 MHz bandwidth second-order ΔΣ time-to-digital converter with gated switched-ring oscillator', IEEE Trans. Circuits Syst. I, vol. 61, no. 8, pp. 2281-2289, 2014. [14] J. H.-L. Lu , M. Inerowicz , S. Joo , J. K. Kwon and B. Jung, 'A low-power, wide-dynamic-range semi-digital universal sensor readout circuit using pulse width modulation', IEEE Sensors J., vol. 11, pp. 1134-1144, 2011. [15] Z. Tan, R. Daamen, A. Humbert, Y. Ponomarev, Y. Chae and M. Pertijs, 'A 1.2-V 8.3-nJ CMOS humidity sensor for RFID applications', IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2469-2477, 2013. [16] H. Ha, D. Sylvester, D. Blaauw and J. Sim, 'A 160 nW 63.9 fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes', IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 220-221. [17] W. Jung, S. Jeong, S. Oh, D. Sylvester and D. Blaauw, 'A 0.7 pF-to-10 nF fully digital capacitance-to-digital converter using iterative delay-chain discharge', IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 484-485. [18] Z. Tan, S. Shalmany, G. Meijer and M. Pertijs, 'An energy-efficient 15-bit capacitive-sensor interface based on period modulation', IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1703-1711, 2012. [19] Y. He, Z. Chang, L. Pakula, S.-H Shalmany and M. Pertijs, ' A 0.05mm2 1V capacitance-to-digital converter based on period modulation', IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 486-487. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7915 | - |
| dc.description.abstract | 此論文中闡述了低功耗的三角積分時間至數位轉換器的設計技巧，以時間暫存器來傳遞時域的量化誤差來達到高解析度的時間至數位轉換器。利用90-nm CMOS製程，所提出的一階三角積分時間至數位轉換器，操作在0.3伏特的情況下，晶片功耗為1.5微瓦，並且在50k赫茲的頻寬內有效位元數(ENOB)為10.9位元。此外，進一步利用相同的設計技巧實現二階的三角積分時間至數位轉換器，並以此時間至數位轉換器應用至電容式感測器介面電路，操作在0.6伏特的情況下，晶片功耗為11微瓦，此電容式感測器介面電路輸入電容範圍為0~5皮法拉，並在2k赫茲的頻寬內效位元數(ENOB)為9.8位元。 | zh_TW |
| dc.description.abstract | The thesis presents low power design techniques for delta-sigma time-to-digital (TDC) converters. By using time register to transfer the time-domain quantization error, the resolution of the TDC can be improved due to noise-shaping of the quantization error. Fabricated in 90-nm CMOS, the first-order delta-sigma TDC consumes a current of 5 uA from a 0.3-V supply. The circuit demonstrates an equivalent number of bits (ENOB) of 10.9 bits in 50 kHz signal bandwidth. Moreover, a capacitance-to-digital (CDC) converter with a second-order delta-sigma TDC is also presented. Consuming 18.4 uA from a 0.6-V supply, the second-order CDC achieves an ENOB of 9.8 bits in 2 kHz signal bandwidth with an input capacitance range of 5 pF. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-19T17:58:29Z (GMT). No. of bitstreams: 1 ntu-105-R03943042-1.pdf: 1284546 bytes, checksum: a86e1c91af2f22ea67df94a673ce9c24 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 致謝 i
摘要 vii Abstract ix Contents xi List of Figure xiv List of Tables xvii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis organization 2 Chapter 2 Background 3 2.1 Applications 3 2.2 Performance metrics of TDC 6 2.2.1 Static performance 6 2.2.2 Dynamics performance 7 2.2.3 Counting rate and dead time 9 2.3 General TDC architecture 10 2.4 Delta-sigma TDC 16 Chapter 3 A Noise-Shaping Time-to-Digital Converter with Gated-Free Ring Oscillator 24 3.1 Introduction 24 3.2 Proposed delta-sigma TDC 25 3.2.1 Conventional gated ring oscillator TDC 25 3.2.2 Proposed delta-sigma TDC 27 3.3 Circuit implementation 29 3.3.1 Time Register 29 3.3.2 Leakage Suppression Switches 30 3.3.3 Gated-free ring oscillator 31 3.3.4 Noise analysis 32 3.4 Experimental Results 35 3.4.1 Measurement at 0.3-V supply voltage 35 3.4.2 Measurement at 0.6-V supply voltage 39 3.5 Conclusion 43 Chapter 4 Time-Mode Capacitive Sensor Interface with Second-Order DS Time-to-Digital Converter 45 4.1 Introduction 45 4.2 Proposed capacitance-to-digital converter 47 4.2.1 1-1 MASH DS TDC 47 4.2.2 Proposed second-order DS TDC 50 4.2.3 Capacitance-to-time converter 53 4.3 Circuit implementation 55 4.3.1 Gated switched-ring oscillator 55 4.3.2 Quantization error generator 56 4.3.3 Gate-delay buffers 57 4.4 Experimental Results 60 4.5 Conclusion 64 Chapter 5 Conclusion 65 Reference 67 | |
| dc.language.iso | en | |
| dc.title | 低功耗三角積分時間至數位轉換器 | zh_TW |
| dc.title | Delta-Sigma Time-to-Digital Converters for Low Power Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 郭建男,邱煥凱 | |
| dc.subject.keyword | 低功耗,時域,超取樣,雜訊整形, | zh_TW |
| dc.subject.keyword | low power,time mode,oversampling,noise shaping, | en |
| dc.relation.page | 69 | |
| dc.identifier.doi | 10.6342/NTU201601745 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2016-08-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-105-1.pdf | 1.25 MB | Adobe PDF | 檢視/開啟 |
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