一個每秒一千萬次取樣重複利用最低有效位元電容次區間架構之雜訊整形連續漸進式類比至數位轉換器

Abstract

本論文提出了一個重複利用最低有效位元電容的次區間新架構，來實現一個雜訊整形連續漸進式類比數位轉換器。 雜訊整形連續漸進式類比數位轉換器當中，必須用一些電容來儲存前幾筆資料的殘值電壓，來實現多樣的雜訊轉移函數。然而，如果需要採用帶有迴避切換演算法的次區間架構，來減少電容式數位至類比轉換器的切換功耗，則會需要一個額外的輔助類比數位轉換器而占用更多的面積，亦會提高電路的設計複雜度。在這裡提出的重複利用最低有效位元電容的新架構中，我們把這些殘值儲存電容也同時作為粗解用的數位至類比傳換器，便可以有效解決這種麻煩的狀況。 為了更提升電路的精準度，我們利用了一個新的分數殘值電壓生成方法，將跟蹤切換的技巧與雜訊整形融合。迴避與偵測以及對齊式切換技巧也在這個作品中使用來降低切換耗能。 本文所提出的類比數位轉換使用40奈米CMOS製程實現。在0.9V的供電下，所消耗的功耗是62.3微瓦，量測得頻寬內最高的信號與雜訊諧波比為68dB，等效為168dB的Schreier 效能指標。

This thesis presents a 10 MS/s noise shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) based on a new LSB-cap-reusing sub-range architecture. To implement various noise transfer functions (NTFs), there must be some capacitors keeping the residue voltage of prior conversions in NS-SAR ADCs. In the meanwhile, if the sub-range architecture with a skipping algorithm is going to be adopted to reduce the capacitive digital-to-analog converter (CDAC) switching power, another assisting ADC will be needed, which occupies more area and increases the circuit complexity. The proposed new LSB-cap-reusing architecture can easily solve the troublesome situation by reusing the residue-storing LSB capacitors as the coarse DACs. To further increase the accuracy, the tracking average algorithm is combined with NS in this design with a new fractional residue generating scheme. The detect-and-skip (DAS) algorithm and the aligned switching (AS) techniques are also introduced to lower the switching energy. The proposed NS-SAR ADC is fabricated in a 40-nm CMOS process. It consumes 62.3μW under a 0.9-V supply. The measured in-band peak SNDR is 68 dB, which is equivalent to a Schreier figure-of-merit of 168 dB.