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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78845完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Wei-Jyun Wang | en |
| dc.contributor.author | 王維駿 | zh_TW |
| dc.date.accessioned | 2021-07-11T15:23:37Z | - |
| dc.date.available | 2022-02-13 | |
| dc.date.copyright | 2019-02-13 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-01-29 | |
| dc.identifier.citation | [1] J. A. Fredenburg and M. P. Flynn, 'A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC,' in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2898-2904, Dec. 2012.
[2] Z. Chen, M. Miyahara and A. Matsuzawa, 'A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC,' 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C64-C65. [3] Z. Chen, M. Miyahara and A. Matsuzawa, 'A 2ndorder fully-passive noise-shaping SAR ADC with embedded passive gain,' 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, 2016, pp. 309-312. [4] Y. Shu, L. Kuo and T. Lo, 'An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928-2940, Dec. 2016. [5] W. Guo and N. Sun, 'A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator,' ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, 2016, pp. 405-408. [6] C. Liu and M. Huang, '28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter,' 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 466-467. [7] Y. Lin, C. Tsai, S. Tsou, R. Chu and C. Lu, 'A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C234-C235. [8] W. Guo, H. Zhuang and N. Sun, 'A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C236-C237. [9] S. Li, B. Qiao, M. Gandara and N. Sun, 'A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure,' 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 234-236. [10] Z. Chen, M. Miyahara and A. Matsuzawa, 'A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder,' ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, 2016, pp. 249-252. [11] You-Kuang Chang, Chao-Shiun Wang and Chorng-Kuang Wang, 'A 8-bit 500-KS/s low power SAR ADC for bio-medical applications,' 2007 IEEE Asian Solid-State Circuits Conference, Jeju, 2007, pp. 228-231. [12] V. Hariprasath, J. Guerber, S. -. Lee and U. -. Moon, 'Merged capacitor switching based SAR ADC with highest switching energy-efficiency,' in Electronics Letters, vol. 46, no. 9, pp. 620-621, 29 April 2010. [13] Y. Zhu et al., 'A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010. [14] B. P. Ginsburg and A. P. Chandrakasan, 'An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,' 2005 IEEE International Symposium on Circuits and Systems, Kobe, 2005, pp. 184-187 Vol. 1. [15] B. P. Ginsburg and A. P. Chandrakasan, '500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,' in IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739-747, April 2007. [16] C. Liu, S. Chang, G. Huang and Y. Lin, 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [17] H. Tai, Y. Hu, H. Chen and H. Chen, '11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 196-197. [18] S. Hsieh and C. Hsieh, 'A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC,' 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. [19] Y. Hu, K. Lin and H. Chen, 'A 510nW 12-bit 200kS/s SAR-assisted SAR ADC using a re-switching technique,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C238-C239. [20] W. Liu, P. Huang and Y. Chiu, 'A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR,' 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, 2010, pp. 380-381. [21] W. Tseng, et al., 'A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters,' in IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2222-2231, Oct. 2016 [22] Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, 'A low-noise self-calibrating dynamic comparator for high-speed ADCs,' 2008 IEEE Asian Solid-State Circuits Conference, Fukuoka, 2008, pp. 269-272. [23] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, 'A 10-bit Charge-Redistribution ADC Consuming 1.9μW at 1 MS/s,' in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [24] T. Sepke, P. Holloway, C. G. Sodini, and H. S. Lee, “Noise analysis for comparator-based circuits,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, no. 3, pp. 541–553, Mar. 2 [25] D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl and B. Nauta, 'A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time,' 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, San Francisco, CA, 2007, pp. 314-605. [26] P. Harpe, E. Cantatore and A. van Roermund, 'A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step,' in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3011-3018, Dec. 2013. [27] P. Harpe, E. Cantatore and A. van Roermund, '11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 194-195. [28] T. Miki et al., 'A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques,' in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, June 2015. [29] C. Liu, M. Huang and Y. Tu, 'A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC,' in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2941-2950, Dec. 2016. [30] Y. Chen, K. Chang and C. Hsieh, 'A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 51, no. 2, pp. 357-364, Feb. 2016. [31] J. Muhlestein, S. Leuenberger, H. Sun, Y. Xu and U. Moon, 'A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization,' 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, pp. 1-4. [32] A. Sanyal, K. Ragab, L. Chen, T. R. Viswanathan, S. Yan and N. Sun, 'A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping,' Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, San Jose, CA, 2014, pp. 1-4. [33] S. Hsieh and C. Hsieh, 'A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator,' 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 240-242. [34] Y. Zhu, C. Chan, S. U and R. P. Martins, 'An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1223-1234, May 2016. [35] F. van der Goes et al., '11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 200-201. [36] Fen-Jen Chiang, 'All Digital Calibration for High-resolution Successive-Approximation Register Analog-to-Digital Converter', unpublished master thesis, National Taiwan University, Taipei, Taiwan, Feb 2019. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78845 | - |
| dc.description.abstract | 本論文提出了一個重複利用最低有效位元電容的次區間新架構，來實現一個雜訊整形連續漸進式類比數位轉換器。
雜訊整形連續漸進式類比數位轉換器當中，必須用一些電容來儲存前幾筆資料的殘值電壓，來實現多樣的雜訊轉移函數。然而，如果需要採用帶有迴避切換演算法的次區間架構，來減少電容式數位至類比轉換器的切換功耗，則會需要一個額外的輔助類比數位轉換器而占用更多的面積，亦會提高電路的設計複雜度。在這裡提出的重複利用最低有效位元電容的新架構中，我們把這些殘值儲存電容也同時作為粗解用的數位至類比傳換器，便可以有效解決這種麻煩的狀況。 為了更提升電路的精準度，我們利用了一個新的分數殘值電壓生成方法，將跟蹤切換的技巧與雜訊整形融合。迴避與偵測以及對齊式切換技巧也在這個作品中使用來降低切換耗能。 本文所提出的類比數位轉換使用40奈米CMOS製程實現。在0.9V的供電下，所消耗的功耗是62.3微瓦，量測得頻寬內最高的信號與雜訊諧波比為68dB，等效為168dB的Schreier 效能指標。 | zh_TW |
| dc.description.abstract | This thesis presents a 10 MS/s noise shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) based on a new LSB-cap-reusing sub-range architecture.
To implement various noise transfer functions (NTFs), there must be some capacitors keeping the residue voltage of prior conversions in NS-SAR ADCs. In the meanwhile, if the sub-range architecture with a skipping algorithm is going to be adopted to reduce the capacitive digital-to-analog converter (CDAC) switching power, another assisting ADC will be needed, which occupies more area and increases the circuit complexity. The proposed new LSB-cap-reusing architecture can easily solve the troublesome situation by reusing the residue-storing LSB capacitors as the coarse DACs. To further increase the accuracy, the tracking average algorithm is combined with NS in this design with a new fractional residue generating scheme. The detect-and-skip (DAS) algorithm and the aligned switching (AS) techniques are also introduced to lower the switching energy. The proposed NS-SAR ADC is fabricated in a 40-nm CMOS process. It consumes 62.3μW under a 0.9-V supply. The measured in-band peak SNDR is 68 dB, which is equivalent to a Schreier figure-of-merit of 168 dB. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T15:23:37Z (GMT). No. of bitstreams: 1 ntu-108-R05943024-1.pdf: 2809315 bytes, checksum: 69217b5d22ba912a4e9486f250ea6547 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 口試委員審定書 I
致謝 II 摘要 III Abstract IV Contents VI List of Figures VIII List of Tables X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of Analog-to-Digital Converter 4 2.1 Introduction 4 2.2 Performance Index 5 2.2.1 Static Performance 5 2.2.2 Dynamic Performance 8 2.3 Basic ADC Architectures 13 2.3.1 Flash ADC 13 2.3.2 Pipelined ADC 14 2.3.3 Successive Approximation Register ADC (SAR ADC) 16 2.3.4 Sigma-Delta ADC 17 2.3.5 Two-step and Sub-range ADC 19 Chapter 3 High Resolution, Low-Power SAR ADC Design 21 3.1 Introduction 21 3.2 Capacitive DAC 21 3.2.1 Thermal Noise 21 3.2.2 Capacitor Mismatch 22 3.2.3 Switching power 24 3.3 Comparator 26 3.3.1 Noise 27 3.3.2 Offset 30 3.3.3 Power consumption 32 3.4 Hybrid Architecture 33 3.4.1 Time-domain quantization 33 3.4.2 Integrating conversion 35 3.4.3 Noise shaping technique 36 Chapter 4 A 10MS/s Noise Shaping SAR ADC Based on an LSB-Cap-Reusing Sub-range Architecture 39 4.1 Introduction 39 4.2 Proposed Architecture 41 4.3 Noise Shaping Analysis 45 4.3.1 Quantization Noise Transfer Function (NTF) 45 4.3.2 Noise in passive integration 50 4.3.3 Noise Tradeoff 51 4.4 Circuit Implementation 55 4.4.1 Capacitive-DAC Switching and Noise Reduction Techniques 55 4.4.2 Offset Calibration 61 4.4.3 Design of Key Circuit Blocks 63 Chapter 5 Experiments Results 67 5.1 Environment Setup 67 5.2 Measurement Results 69 Chapter 6 Conclusions 75 Bibliography 76 Appendix 83 | |
| dc.language.iso | en | |
| dc.subject | 偵測和迴避 | zh_TW |
| dc.subject | 雜訊整形 | zh_TW |
| dc.subject | 連續漸進式數位至類比轉換器 | zh_TW |
| dc.subject | 數位至類比轉換器 | zh_TW |
| dc.subject | 最低有效位元電容之重複利用 | zh_TW |
| dc.subject | 跟?切換 | zh_TW |
| dc.subject | Noise shaping | en |
| dc.subject | digital-to-analog converter (DAC) | en |
| dc.subject | LSB-cap-reusing | en |
| dc.subject | tracking average | en |
| dc.subject | detect-and-skip (DAS) | en |
| dc.subject | successive-approximation-register analog-to-digital converter (SAR ADC) | en |
| dc.title | 一個每秒一千萬次取樣重複利用最低有效位元電容次區間架構之雜訊整形連續漸進式類比至數位轉換器 | zh_TW |
| dc.title | A 10MS/s Noise Shaping Successive-Approximation Register Analog-to-Digital Converter Based on an LSB-Cap-Reusing Sub-range Architecture | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 戴宏彥,林宗賢 | |
| dc.subject.keyword | 雜訊整形,連續漸進式數位至類比轉換器,數位至類比轉換器,最低有效位元電容之重複利用,跟?切換,偵測和迴避, | zh_TW |
| dc.subject.keyword | Noise shaping,successive-approximation-register analog-to-digital converter (SAR ADC),digital-to-analog converter (DAC),LSB-cap-reusing,tracking average,detect-and-skip (DAS), | en |
| dc.relation.page | 84 | |
| dc.identifier.doi | 10.6342/NTU201900298 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-01-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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