使用電漿增強型原子層沉積技術成長高介電係數氧化層電容元件及負電容之研究

Abstract

本論文主要分為三個章節，首先第一章在介紹關於原子層沉積(atomic layer deposition，ALD)機台參數上的調整，從purge time的變化、上腔體溫度的改變、及載台溫度的調控，均可以發現對薄膜沉積有一定的影響，進而改變高介電係數介電層的電性特徵，我們需要找出機台目前的最佳參數，在進行後續的實驗。第二章介紹電漿處理，在一般thermal mode ALD薄膜成長的狀態下，利用電漿處理，可以大幅改善高介電係數氧化層電容元件之效能。第三章則在研究負電容效應，根據電容串連公式可以知道兩個電容串連時，其總電容值會下降，但我們研究發現利用順電性與鐵電性串聯的介電層，可以觀察到電容放大的現象。

This paper is divided into three chapters. First, the first chapter introduces the adjustment of process parameters of atomic layer deposition (ALD). The variations of the purge time and the temperatures of the upper chamber as well as the sample stage, result in the impact on the quality and electrical characteristics of the deposited high-K gate dielectrics. In the second chapter, the plasma treatment was introduced in the ALD process. The deposited high-K gate dielectrics exhibited the great improvement in the electrical characteristics due to the plasma treatment. In the third chapter, the ferroelectric negative capacitance was investigated. It is well recognized that the capacitance of two capacitors in series is smaller than the individual capacitance of the capacitors. However, the capacitance enhancement was observed in this study if a paraelectric capacitor was in series with a ferroelectric capacitor, revealing the negative capacitance effect in the ferrolectric layer.