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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳敏璋(Miin-Jang Chen) | |
| dc.contributor.author | I-Na Tsai | en |
| dc.contributor.author | 蔡依娜 | zh_TW |
| dc.date.accessioned | 2021-07-11T14:37:08Z | - |
| dc.date.available | 2022-08-30 | |
| dc.date.copyright | 2017-08-30 | |
| dc.date.issued | 2017 | |
| dc.date.submitted | 2017-08-14 | |
| dc.identifier.citation | 第一章
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M.; O’Neill, A., Experimental observation of negative capacitance in ferroelectrics at room temperature. Nano letters 2014, 14 (7), 3864-3868. 2. Kalinin, S. V.; Morozovska, A. N.; Chen, L. Q.; Rodriguez, B. J., Local polarization dynamics in ferroelectric materials. Reports on Progress in Physics 2010, 73 (5), 056502. 3. Krowne, C.; Kirchoefer, S.; Chang, W.; Pond, J.; Alldredge, L., Examination of the possibility of negative capacitance using ferroelectric materials in solid state electronic devices. Nano letters 2011, 11 (3), 988-992. 4. Salahuddin, S.; Datta, S. In Can the subthreshold swing in a classical FET be lowered below 60 mV/decade?, Electron Devices Meeting, 2008. IEDM 2008. IEEE International, IEEE: 2008; pp 1-4. 5. Salahuddin, S.; Datta, S., Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano letters 2008, 8 (2), 405-410. 6. Jain, A.; Alam, M. A., Stability constraints define the minimum subthreshold swing of a negative capacitance field-effect transistor. IEEE Transactions on Electron Devices 2014, 61 (7), 2235-2242. 7. Müller, J.; Böscke, T. S.; Schröder, U.; Mueller, S.; Bräuhaus, D.; Böttger, U.; Frey, L.; Mikolajick, T., Ferroelectricity in simple binary ZrO2 and HfO2. Nano letters 2012, 12 (8), 4318-4323. 8. Ruh, R.; Garrett, H.; Domagala, R.; Tallan, N., The Svstern Zirconia‐Hafnia. Journal of the American Ceramic Society 1968, 51 (1), 23-28. 9. Lin, B.-T.; Lu, Y.-W.; Shieh, J.; Chen, M.-J., Induction of ferroelectricity in nanoscale ZrO 2 thin films on Pt electrode without post-annealing. Journal of the European Ceramic Society 2017, 37 (3), 1135-1139. 10. Islam Khan, A.; Bhowmik, D.; Yu, P.; Joo Kim, S.; Pan, X.; Ramesh, R.; Salahuddin, S., Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures. Applied Physics Letters 2011, 99 (11), 113501. 11. Uchino, K., Ferroelectric Devices 2nd Edition. CRC press: 2009. 12. Bertaud, T.; Bermond, C.; Lacrevaz, T.; Vallée, C.; Morand, Y.; Fléchet, B.; Farcy, A.; Gros-Jean, M.; Blonkowski, S., Wideband frequency and in situ characterization of ultra thin ZrO 2 and HfO 2 films for integrated MIM capacitors. Microelectronic Engineering 2010, 87 (3), 301-305. 13. Jonscher, A. K., Dielectric relaxation in solids. Journal of Physics D: Applied Physics 1999, 32 (14), R57. 14. Tao, J.; Zhao, C.; Zhao, C.; Taechakumput, P.; Werner, M.; Taylor, S.; Chalker, P., Extrinsic and intrinsic frequency dispersion of high-k materials in capacitance-voltage measurements. Materials 2012, 5 (6), 1005-1032. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77906 | - |
| dc.description.abstract | 本論文主要分為三個章節，首先第一章在介紹關於原子層沉積(atomic layer deposition，ALD)機台參數上的調整，從purge time的變化、上腔體溫度的改變、及載台溫度的調控，均可以發現對薄膜沉積有一定的影響，進而改變高介電係數介電層的電性特徵，我們需要找出機台目前的最佳參數，在進行後續的實驗。第二章介紹電漿處理，在一般thermal mode ALD薄膜成長的狀態下，利用電漿處理，可以大幅改善高介電係數氧化層電容元件之效能。第三章則在研究負電容效應，根據電容串連公式可以知道兩個電容串連時，其總電容值會下降，但我們研究發現利用順電性與鐵電性串聯的介電層，可以觀察到電容放大的現象。 | zh_TW |
| dc.description.abstract | This paper is divided into three chapters. First, the first chapter introduces the adjustment of process parameters of atomic layer deposition (ALD). The variations of the purge time and the temperatures of the upper chamber as well as the sample stage, result in the impact on the quality and electrical characteristics of the deposited high-K gate dielectrics. In the second chapter, the plasma treatment was introduced in the ALD process. The deposited high-K gate dielectrics exhibited the great improvement in the electrical characteristics due to the plasma treatment. In the third chapter, the ferroelectric negative capacitance was investigated. It is well recognized that the capacitance of two capacitors in series is smaller than the individual capacitance of the capacitors. However, the capacitance enhancement was observed in this study if a paraelectric capacitor was in series with a ferroelectric capacitor, revealing the negative capacitance effect in the ferrolectric layer. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T14:37:08Z (GMT). No. of bitstreams: 1 ntu-106-R04527046-1.pdf: 4098112 bytes, checksum: 07a65ad3233429fc0c57350ad3fbafe0 (MD5) Previous issue date: 2017 | en |
| dc.description.tableofcontents | 目錄
致謝 ...................................................................................................I 摘要 ..................................................................................................II Abstract ................................................................................................III 目錄 ................................................................................................IV 圖目錄 ................................................................................................VI 表目錄 ................................................................................................X 第一章 簡介 1 1.1 研究動機 1 1.2 高介電係數(High K)材料 2 1.3 原子層沉積技術(ALD) 4 1.3.1 原子層沉積技術 4 1.3.2 電漿輔助原子層沉積技術 8 1.4 鐵電負電容 11 1.5 論文導覽 14 1.6 參考文獻 16 第二章 原子層沉積製程參數之調整 17 2.1 簡介 17 2.2 實驗步驟 18 2.2.1 TDMAZ、TDMAH前驅物介紹 21 2.3 實驗結果與討論 23 2.3.1 Purge time改變 23 2.3.2 調整上腔體溫度 26 2.3.3 調整載台溫度 28 2.4 結論 32 2.5 參考文獻 33 第三章 電漿處理對高介電係數氧化層電容元件電性表現的影響 34 3.1 簡介 34 3.2 實驗步驟 35 3.3 實驗結果與討論 43 3.3.1 薄膜厚度分析 43 3.3.2 電漿處理 46 3.4 結論 53 3.5 參考文獻 54 第四章 鐵電負電容元件之研究 55 4.1 鐵電材料之簡介 55 4.2 實驗步驟 58 4.2.1 順電層材料之成長 58 4.2.2 鐵電層材料之成長 61 4.3 實驗結果與討論 63 4.3.1 順電層材料調整 63 4.3.2 鐵電層調整 68 4.4 結論 78 4.5 參考文獻 80 第五章 總結 82 | |
| dc.language.iso | zh-TW | |
| dc.title | 使用電漿增強型原子層沉積技術成長高介電係數氧化層電容元件及負電容之研究 | zh_TW |
| dc.title | High-K Dielectrics and Ferroelectric Negative Capacitance Prepared by Plasma Enhanced Atomic Layer Deposition | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 廖洺漢(Ming-Han Liao),吳肇欣(Chao-Hsin Wu),李峻霣(Jiun-Yun Li) | |
| dc.subject.keyword | 原子層沉積技術,二氧化鋯,二氧化鉿,電漿處理,負電容, | zh_TW |
| dc.subject.keyword | Atomic layer deposition (ALD),zirconium dioxide (ZrO2),hafnium dioxide (HfO_2),negative capacitance,plasma treatment, | en |
| dc.relation.page | 83 | |
| dc.identifier.doi | 10.6342/NTU201702763 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2017-08-14 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
| 顯示於系所單位： | 材料科學與工程學系 | |
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