毫米波頻帶之38-GHz 65-nm CMOS與 60-GHz 28-nm CMOS功率放大器研究

Abstract

此篇論文提出了在65-nm GP CMOS製程中設計寬頻數位調變之類比預失真38 GHz功率放大器以及在28-nm LP CMOS製程中設計60 GHz之線性功率放大器，探討在先進製程中電晶體佈局對整體電路的重要性。

在38 GHz功率放大器中，輸出級採用了兩路的變壓器功率整合來進行匹配，屬於電流式的功率疊加架構。在 驅動 級 (driver stage)的設計中，偏壓在深度的AB類放大器作為 AM-AM的預失真補償器，使得增益壓縮一分貝輸出功率(OP1dB)進一步的推近飽和輸出功率(並具有改善三階項調變失真(IMD3)的效果。而在AM-PM的預失真設計中，採用了PMOS電容來補償驅動級的輸入端非線性電容來降低的AM-PM的失真度。在連續波的量測中，此項功率放大器具有34至41 GHz之小訊號增益頻寬，並在39 GHz達到了35%的最大功率附加效率(PAEmax)以及20.7的飽和輸出功率(Psat)。在64QAM OFDM載波頻率為34-41 GHz的調變訊號量測中，此項功率放大器在1600 MHz的調變頻寬與-25 dB EVM下達到了13.2 dBm的輸出功率，以及6.98Gb/s的資料率。

在60 GHz功率放大器設計中，採用了不同的電晶體佈局方式進行測試，來降低電晶體裝置上的寄生效應，例如:RG、RS、RD。此項功率放大器輸出級採用了兩路的變壓器功率整合來進行匹配，屬於電流式的功率疊加架構。驅動級以及輸出級皆偏壓在class-A的區域來達到較高的功率增益。最後在小訊號的量測中項對於TSMC傳統的電晶體佈局，此項論文所運用的電晶體佈局達到了更高的功率增益。在小訊號的量測中，此項功率放大器在63 GHz達到了17.5 dB的功率增益。在大訊號量測中，此項功率放大器在65 GHz達到了達到了17.3 dBm的的Psat以及17.3%的PAEmax。

A 38 GHz transformer-based high linear power amplifier for wideband 64-QAM OFDM modulated signal by using analog pre-distortion in 65-nm CMOS process and a 60 GHz transformer-based linear power amplifier with layout improvement device are presented in this paper.

In 38 GHz power amplifier, the output power is based on the two-way transformer current combining structure. The driver amplifier which is biased in deep class-AB acts as an AM-AM pre-distorter to make 1-dB gain compression output power (OP1dB) ap-proach saturated output power (Psat) and improve the third-order intermodulation distor-tion (IMD3) by the technique of third-order transconductance cancellation. Also a PMOS capacitor is used to improve the AM-PM distortion by compensating the nonlinear capac-itor at the driver stage. In the continuous-wave measurement, this power amplifier achieves a 3-dB small-signal bandwidth from 34 to 41 GHz with 20.7-dBm peak Psat, 35% peak PAEmax, 20.2-dBm peak OP1dB, and 32.8% peak PAE1dB at 39 GHz. In the 64-QAM OFDM modulated signal measurement, this power amplifier can transmit 1600-MHz channel bandwidth in each carrier frequency from 35-41 GHz and achieves 13.2-dBm output power at 38-GHz carrier frequency under the EVM less than -25 dB. The transmission data rate of the proposed power amplifier reaches up to 6.98-Gb/s from 35-41 GHz.

In 60 GHz transformer-based linear power amplifier, design a different device layout to lower the parasitic loss such as RG, RD, and RS. The output power is also based on the two-way transformer current combining structure. The driver amplifier and power ampli-fier are biased in class-A to get larger power gain. Finally, in the small-signal measure-ment results, compare to the TSMC device layout, the power amplifier with the proposed device layout get higher power gain in the 60-GHz band. In the small-signal measurement, this power amplifier achieves 17.4-dB small-signal power gain at 65 GHz. In the large-siganl measurement, this power amplifier achieves 17.3-dBm peak Psat and 17.3% peak PAEmax at 65 GHz.