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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77295完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃天偉 | zh_TW |
| dc.contributor.author | 陳育群 | zh_TW |
| dc.contributor.author | Yu-Chun Chen | en |
| dc.date.accessioned | 2021-07-10T21:54:38Z | - |
| dc.date.available | 2024-08-15 | - |
| dc.date.copyright | 2019-08-19 | - |
| dc.date.issued | 2019 | - |
| dc.date.submitted | 2002-01-01 | - |
| dc.identifier.citation | [1] S. Shakib, H.-C. Park, J. Dunworth, V. Aparin, and K. Entesari, “A highly efficient and linear power amplifier for 28-GHz 5G phased array radios in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 3020–3036, Dec. 2016.
[2] M. Vigilante and P. Reynaert, “A wideband class-AB power amplifier with 29–57-GHz AM–PM compensation in 0.9-V 28-nm bulk CMOS,” IEEE J. Solid-State Cir-cuits, vol. 53, no. 5, pp. 1288-1301, May 2018. [3] S. Shakib, M. Elkholy, J. Dunworth, V. Aparin and K. Entesari, “A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 44-45. [4] C. Fager, J. C. Pedro, N. B. de Carvalho, H. Zirath, F. Fortes and M. J. Rosario, “A comprehensive analysis of IMD behavior in RF CMOS power amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 24-34, Jan. 2004. [5] C. Wang, L. E. Larson and P. M. Asbeck, “A nonlinear capacitance cancellation tech-nique and its application to a CMOS class AB power amplifier,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), May 2001, pp. 39-42. [6] B. Park, Daechul Jeong, J. Kim, Y. Cho, Kyunghoon Moon and B. Kim, “Highly linear CMOS power amplifier for mm-wave applications,” in IEEE MTT-S Int. Mi-crow. Symp. Dig., May 2016, pp. 1-3. [7] S. N. Ali, P. Agarwal, J. Baylon, S. Gopal, L. Renaud and D. Heo, “A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2018, pp. 406-408. [8] H. Jia, C. C. Prawoto, B. Chi, Z. Wang and C. P. Yue, “A full Ka-Band power am-plifier with 32.9% PAE and 15.3-dBm power in 65-nm CMOS,” IEEE Trans. Cir-cuits Syst. I, Reg. Papers, vol. 65, no. 9, pp. 2657-2668, Sept. 2018. [9] Y. Zhang and P. Reynaert, “A high-efficiency linear power amplifier for 28GHz mo-bile communications in 40nm CMOS,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Jun. 2017, pp. 33-36. [10] J. P. Martins, P. M. Cabral, N. Borges Carvalho and J. C. Pedro, “A metric for the quantification of memory effects in power amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 12, pp. 4432-4439, Dec. 2006. [11] S. N. Ali et al., “A 40% PAE frequency-reconfigurable CMOS power amplifier with tunable Gate–Drain neutralization for 28-GHz 5G Radios,” IEEE Trans. Microw. Theory Techn., vol. 66, no. 5, pp. 2231-2245, May 2018. [12] T. Li and H. Wang, “A continuous-mode 23.5-41GHz hybrid class-F/F-l power am-plifier with 46% peak PAE for 5G massive MIMO applications,” in Proc. IEEE Ra-dio Freq. Integr. Circuits Symp. (RFIC), Jun. 2018, pp. 220-230. [13] S. Chang, C. Chen and H. Wang, “A Ka-Band dual-mode power amplifier in 65-nm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 28, no. 8, pp. 708-710, Aug. 2018. [14] C.-W. Wu, et al., “Design of a 60-GHz high-output power stacked- FET power am-plifier using transformer-based voltage-type power combining in 65-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 66, no. 10, pp. 4595-4607, Oct. 2018. [15] J.-F. Yeh, et al., “MMW ultra-compact n-way transformer PAs using bowtie-radial architecture in 65-nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 25, no. 7, pp. 460-462, Jul. 2015. [16] C.-F. Chou, et al., “Design of a V-band 20-dBm wideband power amplifier using transformer-based radial power combining in 90-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 64, no. 12, pp. 4545-4560, Dec. 2016. [17] D. Zhao and P. Reynaert, “A 60-GHz dual-mode Class AB power amplifier in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2323-2337, Oct. 2013. [18] M. Bassi, et al., “A 40–67 GHz power amplifier with 13 dBm Psat and 16% PAE in 28 nm CMOS LP,” IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1618-1628, Jul. 2015. [19] Y.-H. Hsiao, et al., “Millimeter-wave CMOS power amplifiers with high output power and wideband performances,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 12, pp. 4520-4533, Dec. 2013. [20] S.-M. Weng, et al., “A 60-GHz adaptively biased power amplifier with predistortion linearizer in 90-nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2018, pp. 651-654. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77295 | - |
| dc.description.abstract | 此篇論文提出了在65-nm GP CMOS製程中設計寬頻數位調變之類比預失真38 GHz功率放大器以及在28-nm LP CMOS製程中設計60 GHz之線性功率放大器，探討在先進製程中電晶體佈局對整體電路的重要性。
在38 GHz功率放大器中，輸出級採用了兩路的變壓器功率整合來進行匹配，屬於電流式的功率疊加架構。在 驅動 級 (driver stage)的設計中，偏壓在深度的AB類放大器作為 AM-AM的預失真補償器，使得增益壓縮一分貝輸出功率(OP1dB)進一步的推近飽和輸出功率(並具有改善三階項調變失真(IMD3)的效果。而在AM-PM的預失真設計中，採用了PMOS電容來補償驅動級的輸入端非線性電容來降低的AM-PM的失真度。在連續波的量測中，此項功率放大器具有34至41 GHz之小訊號增益頻寬，並在39 GHz達到了35%的最大功率附加效率(PAEmax)以及20.7的飽和輸出功率(Psat)。在64QAM OFDM載波頻率為34-41 GHz的調變訊號量測中，此項功率放大器在1600 MHz的調變頻寬與-25 dB EVM下達到了13.2 dBm的輸出功率，以及6.98Gb/s的資料率。 在60 GHz功率放大器設計中，採用了不同的電晶體佈局方式進行測試，來降低電晶體裝置上的寄生效應，例如:RG、RS、RD。此項功率放大器輸出級採用了兩路的變壓器功率整合來進行匹配，屬於電流式的功率疊加架構。驅動級以及輸出級皆偏壓在class-A的區域來達到較高的功率增益。最後在小訊號的量測中項對於TSMC傳統的電晶體佈局，此項論文所運用的電晶體佈局達到了更高的功率增益。在小訊號的量測中，此項功率放大器在63 GHz達到了17.5 dB的功率增益。在大訊號量測中，此項功率放大器在65 GHz達到了達到了17.3 dBm的的Psat以及17.3%的PAEmax。 | zh_TW |
| dc.description.abstract | A 38 GHz transformer-based high linear power amplifier for wideband 64-QAM OFDM modulated signal by using analog pre-distortion in 65-nm CMOS process and a 60 GHz transformer-based linear power amplifier with layout improvement device are presented in this paper.
In 38 GHz power amplifier, the output power is based on the two-way transformer current combining structure. The driver amplifier which is biased in deep class-AB acts as an AM-AM pre-distorter to make 1-dB gain compression output power (OP1dB) ap-proach saturated output power (Psat) and improve the third-order intermodulation distor-tion (IMD3) by the technique of third-order transconductance cancellation. Also a PMOS capacitor is used to improve the AM-PM distortion by compensating the nonlinear capac-itor at the driver stage. In the continuous-wave measurement, this power amplifier achieves a 3-dB small-signal bandwidth from 34 to 41 GHz with 20.7-dBm peak Psat, 35% peak PAEmax, 20.2-dBm peak OP1dB, and 32.8% peak PAE1dB at 39 GHz. In the 64-QAM OFDM modulated signal measurement, this power amplifier can transmit 1600-MHz channel bandwidth in each carrier frequency from 35-41 GHz and achieves 13.2-dBm output power at 38-GHz carrier frequency under the EVM less than -25 dB. The transmission data rate of the proposed power amplifier reaches up to 6.98-Gb/s from 35-41 GHz. In 60 GHz transformer-based linear power amplifier, design a different device layout to lower the parasitic loss such as RG, RD, and RS. The output power is also based on the two-way transformer current combining structure. The driver amplifier and power ampli-fier are biased in class-A to get larger power gain. Finally, in the small-signal measure-ment results, compare to the TSMC device layout, the power amplifier with the proposed device layout get higher power gain in the 60-GHz band. In the small-signal measurement, this power amplifier achieves 17.4-dB small-signal power gain at 65 GHz. In the large-siganl measurement, this power amplifier achieves 17.3-dBm peak Psat and 17.3% peak PAEmax at 65 GHz. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-10T21:54:38Z (GMT). No. of bitstreams: 1 ntu-108-R06942023-1.pdf: 13728811 bytes, checksum: 1d483c80804f1caa1210310a735645f4 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 誌謝 ii
中文摘要 iv ABSTRACT vi CONTENTS viii LIST OF FIGURES x LIST OF TABLES xvi Chapter 1 Introduction 17 1.1 Background and Motivation 17 1.2 Thesis Organization 19 Chapter 2 Design of 38-GHz Power Amplifiers in 65-nm GP CMOS process 20 2.1 Introduction 20 2.2 Circuit Design 21 2.2.1 Proposed Power Amplifier Architecture 21 2.2.2 Device Analysis of the Power Stage 24 2.2.3 Output Stage Design 28 2.2.4 Analog Pre-distortion 29 2.2.5 Simulation Results 35 2.2.6 Chip Photo and Chip Layout 39 2.3 Experimental Results 41 2.3.1 Continuous-wave Measurement Results 41 2.3.2 Modulated Signal Measurement Results 45 2.3.3 Comparison Table 65 2.3.4 Discussion 67 Chapter 3 Design of V-Band Power Amplifiers in 28-nm LP CMOS process 73 3.1 Introduction 73 3.2 Circuit Design 73 3.2.1 Circuit Architecture 73 3.2.2 Device Analysis 74 3.2.3 Output Stage Design 79 3.2.4 Matching Network and Bypass Design 82 3.2.5 Simulation Results 88 3.2.6 Chip Photo and Chip Layout 90 3.3 Experimental Results 93 3.3.1 Continuous-wave Measurement Results 93 3.3.2 Comparison Table 97 3.3.3 Discussion 98 Chapter 4 Conclusion 99 References 100 | - |
| dc.language.iso | en | - |
| dc.subject | 功率放大器 | zh_TW |
| dc.subject | CMOS | zh_TW |
| dc.subject | 類比預失真 | zh_TW |
| dc.subject | 數位調變 | zh_TW |
| dc.subject | 毫米波 | zh_TW |
| dc.subject | CMOS | en |
| dc.subject | millimeter-wave | en |
| dc.subject | digital modulation | en |
| dc.subject | analog pre-distortion | en |
| dc.subject | power amplifier | en |
| dc.title | 毫米波頻帶之38-GHz 65-nm CMOS與 60-GHz 28-nm CMOS功率放大器研究 | zh_TW |
| dc.title | Research on 38-GHz 65-nm CMOS and 60-GHz 28-nm CMOS Power Amplifier in Millimeter Wave Band | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 107-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 王暉;蔡政翰 | zh_TW |
| dc.contributor.oralexamcommittee | ;; | en |
| dc.subject.keyword | CMOS,毫米波,數位調變,類比預失真,功率放大器, | zh_TW |
| dc.subject.keyword | CMOS,millimeter-wave,digital modulation,analog pre-distortion,power amplifier, | en |
| dc.relation.page | 102 | - |
| dc.identifier.doi | 10.6342/NTU201902698 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2019-08-08 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電信工程學研究所 | - |
| 顯示於系所單位： | 電信工程學研究所 | |
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