低溫成長矽鈍化層於氧化鉿/鍺金氧半之可靠性研究

Abstract

隨著金氧半場效電晶體尺寸不斷微縮，為了因應次五奈米節點以下的元件開發，具備高載子遷移率的材料將作為主要通道使用，以提升載子傳輸速度、降低工作電壓。其中，相較於矽，鍺同時具有較高的電子和電洞遷移率，是目前最具潛力取代傳統矽通道，成為高效能低功耗電晶體的材料。在實驗中，原子層沉積(Atomic Layer Deposition)氧化鋁和分子束磊晶(Molecular Beam Epitaxy)氧化鉿作為閘極氧化層，利用約一奈米矽薄膜去鈍化鍺半導體表面，與一般化學氣相沉積高溫成長不同，矽薄膜在分子束磊晶低溫成長下，能更有效抑制鍺擴散，降低氧化鍺的生成。以鎳(Nickel)作為閘極電極，不僅成功得到優異的電壓-電流特性，漏電流小於4×〖10〗^(-9) A/〖cm〗^2@V_g≈V_fb-1，在適當的退火條件下，成功達到極小的累積區頻率耗散和遲滯現象，透過變溫-電導電壓方式探測介面態位密度(interface state density)，位於(1-3)×〖10〗^11 〖cm〗^(-2) 〖eV〗^(-1)範圍內，優異的介面電性結果，提供一個良好平台探討氧化層缺陷和元件可靠性。首先利用電容遲滯量測方式，探測不同退火條件下氧化層缺陷分布，發現氫氣混和氣體退火能有效降低氧化層缺陷密度，形成較窄的氧化層缺陷分布，在16 MV/cm氧化層電場下仍可成功達到可靠度目標(Neff~3x1010 eV-1cm-2)。此外，長時間(t=1000s)施加外加電壓(Vstress=±2.5V)下，無產生缺陷累積引起漏電流的情況，維持良好的電流-電壓特性。在長時間外加不同電場情況下量測遲滯現象、平帶電壓位移變化，探討氧化層缺陷產生與費米能帶位置關係，受惠於穩定的閘極結構，即便長時間施加外加電場下，仍僅有少量的載子被捕捉於氧化層中，成功證明利用低溫方式成長矽鈍化層於鍺半導體表面能同時得到介面特性及元件可靠度。

The complementary metal-oxide-semiconductor (CMOS) devices beyond the sub-5nm node need channel materials with high carrier mobility to increase on-state current at lower supply voltage and therefore reduce active power dissipation. Ge is a promising material to replace the traditional Si channel because of its high electron and hole mobility. In this work, we have used ALD-Al2O3 and MBE-HfO2 as the gate dielectrics for Ge devices with Si passivation. Compared to CVD growth at relatively high temperature, the Si cap layer deposited by MBE at low temperature (LT) has avoided GeOx formation and may minimize the Ge segregation during the Si deposition. Using nickel as the gate electrode, after appropriate thermal annealing, we obtained excellent capacitance-voltage (C-V) characteristics, having small frequency dispersion at accumulation regime on the LT Si-capped Ge gate stacks. Low interfacial densities of states (Dit) in the range of 1011 em-2eV-1 were extracted by conductance method. The high-quality interface provides a suitable platform to characterize BTI (bias temperature instability) reliability. We utilized the CV-hysteresis method to characterize slow traps in the high-k dielectrics and their distribution. The post metallization forming gas annealing (FGA) has greatly decreased effective oxide trap density (Neff), showing an order of magnitude reduction and a narrower distribution. Our results have met the reliability target (Neff~3x1010 cm-2) at an effective oxide field (Eox) of ~16 MV/cm. In addition, to confirm the oxide stability under long stress time, we measured the stress-induced leakage current (SILC) for 1000s at positive and negative Vstress of ±2.5V, respectively. The small gate leakage current remained unchanged after long stress time, representing the robustness of the gate stack quality. To study the long-term reliability, we have stressed the MOS capacitors for 1000s at various oxide electric fields to study generation of slow oxide traps. In conclusion, we have successfully demonstrated that LT MBE Si-cap has effectively passivated Ge surface without unstable GeOx formation and achieved excellent interface and BTI reliability, simultaneously.