請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77218完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 洪銘輝 | zh_TW |
| dc.contributor.advisor | Minghwei Hong | en |
| dc.contributor.author | 洪毓傑 | zh_TW |
| dc.contributor.author | Yu-Jie Hong | en |
| dc.date.accessioned | 2021-07-10T21:51:22Z | - |
| dc.date.available | 2024-08-20 | - |
| dc.date.copyright | 2019-08-26 | - |
| dc.date.issued | 2019 | - |
| dc.date.submitted | 2002-01-01 | - |
| dc.identifier.citation | 1. J. Bardeen and W. H. Brattain, “The transistor, a semiconductor triode”, Phys. Rev., vol. 74, no. 230, 1948, p. 230.
2. D. Kahng and M. M. Atalla, “Silicon-silicon dioxide field induced surface device”, in IRE-AIEE Solid-State Device Research Conference, MIT, 1960. 3. F. Faggin, T. Klein, and L. Vadasz, “Insulated gate field effect transistor integrated circuits with silicon gates”, IEEE Trans. Electron Devices, vol. 16, no. 2, 1969, p. 236. 4. F. M. Wanlass, and C. T. Sah, “Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes”, in Dig. Techn. P. IEEE International Solid State Circuits Conference (ISSCC), pp. 32-33, 1963. 5. G. E. Moore, "Cramming More Components Onto Integrated Circuits,” Proceedings of the IEEE, vol. 86, no. 1, pp. 82-85, Jan. 1998. 6. V. Chan et al., "High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering," in IEEE International Electron Devices Meeting 2003, Washington, DC, USA, 2003, pp. 3.8.1-3.8.4. 7. T. Ghani et al., "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors," in IEEE International Electron Devices Meeting 2003, Washington, DC, USA, 2003, pp. 11.6.1-11.6.3. 8. S. E. Thompson et al., "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Letters, vol. 25, no. 4, pp. 191-193, April 2004. 9. D. A. Muller et al., “The electronic structure at the atomic scale of ultrathin gate oxides,” Nature, vol. 399, no. 6738, pp. 758-761, 1999. 10. K. Mistry et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," in 2007 IEEE International Electron Devices Meeting, Washington, DC, 2007, pp. 247-250. 11. B. Doyle et al., "Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout," 2003 Symposium on VLSI Technology. In Digest of Technical Papers, Kyoto, Japan, 2003, pp. 133-134. 12. J. Robertson, “High dielectric constant oxides,” Eur. Phys. J. Appl. Phys., vol. 28, no. 3, pp. 265-291, 2004. 13. B. Mohammad et al., “State-of-the-art of metal-oxide memristor devices,” Nanotechnology Reviews, vol. 5, no. 3, pp. 311-329, 2019. 14. M. Lundstrom and Z. Ren, "Essential physics of carrier transport in nanoscale MOSFETs," IEEE Transactions on Electron Devices, vol. 49, no. 1, pp. 133-141, Jan. 2002. 15. K. J. Kuhn, "Considerations for Ultimate CMOS Scaling," IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1813-1828, 2012. 16. Chi On Chui, Hyoungsub Kim, D. Chi, B. B. Triplett, P. C. McIntyre and K. C. Saraswat, "A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate," in Digest. International Electron Devices Meeting,, San Francisco, CA, USA, 2002, pp. 437-440. 17. K. Morii, T. Iwasaki, R. Nakane, M. Takenaka, and S. Takagi, "High performance GeO2/Ge nMOSFETs with source/drain junctions formed by gas phase doping," IEEE Electron Device Letters, vol. 31, no. 10, pp. 1092-1094, Oct. 2010. 18. P. Zimmerman et al., "High performance Ge pMOS devices using a Si-compatible process flow," in 2006 International Electron Devices Meeting, San Francisco, CA, 2006, pp. 1-4. 19. K. Kita et al., "Comprehensive study of GeO2 oxidation, GeO desorption and GeO2-metal interaction -understanding of Ge processing kinetics for perfect interface control-," in 2009 IEEE International Electron Devices Meeting, Baltimore, MD, pp. 1-4, 2009. 20. C. H. Lee, T. Nishimura, N. Saido, K. Nagashio, K. Kita and A. Toriumi, "Record-high electron mobility in Ge n-MOSFETs exceeding Si universality," in 2009 IEEE International Electron Devices Meeting, Baltimore, MD, 2009, pp. 1-4. 21. C. H. Lee, T. Nishimura, K. Nagashio, K. Kita and A. Toriumi, "High-Electron-Mobility Ge/GeO2 n-MOSFETs with Two-Step Oxidation," IEEE Transactions on Electron Devices, vol. 58, no. 5, pp. 1295-1301, 2011. 22. R. Zhang, P. C. Huang, N. Taoka, M. Takenaka and S. Takagi, "High mobility Ge pMOSFETs with 0.7 nm ultrathin EOT using HfO2/Al2O3/GeOx/Ge gate stacks fabricated by plasma post oxidation," in 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, 2012, pp. 161-162. 23. B. Kaczer, J. Franco, J. Mitard, P. J. Roussel, A. Veloso, and G. Groeseneken, “Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs,” Microelectron. Eng., vol. 86, no. 7-9, pp. 1582-1584, 2009. 24. G. Tsutsui et al., "Leakage aware Si/SiGe CMOS FinFET for low power applications," 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, 2018, pp. 87-88. 25. J. Franco et al., "SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 396-404, Jan. 2013. 26. J. Franco et al., "Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO2/HfO2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks," 2013 IEEE International Electron Devices Meeting, Washington, DC, 2013, pp. 15.2.1-15.2.4. 27. J. Franco et al., "NBTI Reliability of SiGe and Ge Channel pMOSFETs with SiO2/HfO2 Dielectric Stack," IEEE Transactions on Device and Materials Reliability, vol. 13, no. 4, pp. 497-506, Dec. 2013. 28. G. Groeseneken et al., "Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions," Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Suzhou, 2013, pp. 41-50. 29. C. Lu et al., “Structural and thermodynamic consideration of metal oxide doped GeO2 for gate stack formation on germanium,” Journal of Applied Physics, vol. 116, no. 17, pp. 174103, 2014. 30. C. Lu et al., “Reliability assessment of germanium gate stacks with promising initial characteristics,” Applied Physics Express, vol. 8, no. 2, pp. 021301, 2015. 31. M. Ke, M. Takenaka and S. Takagi, “Understanding of slow traps generation in plasma oxidation GeOx/Ge MOS interfaces with ALD high-k layers,” 2017 47th European Solid-State Device Research Conference (ESSDERC), Leuven, 2017, pp. 296-299. 32. M. Caymax et al., ”The influence of the epitaxial growth process parameters on layer characteristics and device performance in Si-passivated Ge pMOSFETs,” J. Electrochem, vol. 156, no. 12, 2009, pp. H979-H985. 33. M. Schulz, “Interface states at the SiO2-Si interface,” Surface Science, vol. 132, no. 1-3, pp. 422-455, 1983. 34. Y. C. Cheng, “Electronic states at the silicon-silicon dioxide interface,” Progress in Surface Science, vol. 8, no. 5, 1977. 35. Abhitosh Vais et al., “Impact of starting measurement voltage relative to flat-band voltage position on the capacitance-voltage hysteresis and on the defect characterization of InGaAs/high-k metal-oxide-semiconductor stacks,” Applied Physics Letters, vol. 107, no.22, pp. 223504, 2015. 36. Sensors and Actuators, “Hydrogen sensitive mos-structures: Part 1: Principles and applications,” Sensors and Actuators, vol. 1, pp. 403-426, 1981. 37. E. Bury et al., "Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization," 2013 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 2013, pp. GD.3.1-GD.3.5. 38. R. J. Hillard et. al., “Direct and rapid method for determining flatband voltage from non-equilibrium capacitance voltage data,” Proceedings of the Symposium on Diagnostic Techniques for Semiconductor Materials and Device, pp. 261-274, 1992 39. G. Rzepa et al., “Comphy — A compact-physics framework for unified modeling of BTI,” Microelectronics Reliability, vol. 85, pp. 49-65, 2018 | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77218 | - |
| dc.description.abstract | 隨著金氧半場效電晶體尺寸不斷微縮，為了因應次五奈米節點以下的元件開發，具備高載子遷移率的材料將作為主要通道使用，以提升載子傳輸速度、降低工作電壓。其中，相較於矽，鍺同時具有較高的電子和電洞遷移率，是目前最具潛力取代傳統矽通道，成為高效能低功耗電晶體的材料。在實驗中，原子層沉積(Atomic Layer Deposition)氧化鋁和分子束磊晶(Molecular Beam Epitaxy)氧化鉿作為閘極氧化層，利用約一奈米矽薄膜去鈍化鍺半導體表面，與一般化學氣相沉積高溫成長不同，矽薄膜在分子束磊晶低溫成長下，能更有效抑制鍺擴散，降低氧化鍺的生成。以鎳(Nickel)作為閘極電極，不僅成功得到優異的電壓-電流特性，漏電流小於4×〖10〗^(-9) A/〖cm〗^2@V_g≈V_fb-1，在適當的退火條件下，成功達到極小的累積區頻率耗散和遲滯現象，透過變溫-電導電壓方式探測介面態位密度(interface state density)，位於(1-3)×〖10〗^11 〖cm〗^(-2) 〖eV〗^(-1)範圍內，優異的介面電性結果，提供一個良好平台探討氧化層缺陷和元件可靠性。首先利用電容遲滯量測方式，探測不同退火條件下氧化層缺陷分布，發現氫氣混和氣體退火能有效降低氧化層缺陷密度，形成較窄的氧化層缺陷分布，在16 MV/cm氧化層電場下仍可成功達到可靠度目標(Neff~3x1010 eV-1cm-2)。此外，長時間(t=1000s)施加外加電壓(Vstress=±2.5V)下，無產生缺陷累積引起漏電流的情況，維持良好的電流-電壓特性。在長時間外加不同電場情況下量測遲滯現象、平帶電壓位移變化，探討氧化層缺陷產生與費米能帶位置關係，受惠於穩定的閘極結構，即便長時間施加外加電場下，仍僅有少量的載子被捕捉於氧化層中，成功證明利用低溫方式成長矽鈍化層於鍺半導體表面能同時得到介面特性及元件可靠度。 | zh_TW |
| dc.description.abstract | The complementary metal-oxide-semiconductor (CMOS) devices beyond the sub-5nm node need channel materials with high carrier mobility to increase on-state current at lower supply voltage and therefore reduce active power dissipation. Ge is a promising material to replace the traditional Si channel because of its high electron and hole mobility. In this work, we have used ALD-Al2O3 and MBE-HfO2 as the gate dielectrics for Ge devices with Si passivation. Compared to CVD growth at relatively high temperature, the Si cap layer deposited by MBE at low temperature (LT) has avoided GeOx formation and may minimize the Ge segregation during the Si deposition. Using nickel as the gate electrode, after appropriate thermal annealing, we obtained excellent capacitance-voltage (C-V) characteristics, having small frequency dispersion at accumulation regime on the LT Si-capped Ge gate stacks. Low interfacial densities of states (Dit) in the range of 1011 em-2eV-1 were extracted by conductance method. The high-quality interface provides a suitable platform to characterize BTI (bias temperature instability) reliability. We utilized the CV-hysteresis method to characterize slow traps in the high-k dielectrics and their distribution. The post metallization forming gas annealing (FGA) has greatly decreased effective oxide trap density (Neff), showing an order of magnitude reduction and a narrower distribution. Our results have met the reliability target (Neff~3x1010 cm-2) at an effective oxide field (Eox) of ~16 MV/cm. In addition, to confirm the oxide stability under long stress time, we measured the stress-induced leakage current (SILC) for 1000s at positive and negative Vstress of ±2.5V, respectively. The small gate leakage current remained unchanged after long stress time, representing the robustness of the gate stack quality. To study the long-term reliability, we have stressed the MOS capacitors for 1000s at various oxide electric fields to study generation of slow oxide traps. In conclusion, we have successfully demonstrated that LT MBE Si-cap has effectively passivated Ge surface without unstable GeOx formation and achieved excellent interface and BTI reliability, simultaneously. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-10T21:51:22Z (GMT). No. of bitstreams: 1 ntu-108-R05222032-1.pdf: 3919574 bytes, checksum: 9d98a98404e80571fc9fe65e9813d003 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 論文口試委員審定書 i
謝辭 ii 中文摘要 iii Abstract iv Chapter 1: Introduction 1 1.1 Historical overview 1 1.2 High-k dielectrics 5 1.3 Metal gate electrodes 6 1.4 High performance CMOS devices 6 1.4.1 High mobility materials 6 1.4.2 Advantages of Ge-based CMOS devices 7 1.5 Ge surface passivation and defects 8 1.5.1 Introduction 8 1.5.2 GeO2 passivation 9 1.5.3 Si-passivation 10 1.5.4 BTI reliability of Ge MOS 12 Chapter 2: Experimental procedures 15 2.1 MOS capacitor fabrication 15 2.1.1 Film Deposition in UHV Multi-chamber system 16 2.1.2 Rapid thermal annealing (RTA) 16 2.1.3 Metal electrodes deposition 17 2.1.4 Hydrogen passivation 17 2.2 Electrical characterization 18 2.2.1 Extraction of interface trap Density (Dit) 18 2.2.2 Shallow and Deep oxide defects 22 2.2.3 BTI degradation 23 2.2.4 Accessibility of defect levels with MOS capacitors 24 Chapter 3: Basic electrical properties measurements 26 3.1 Measurement instruments setup 26 3.2 Introduction 26 3.3 Different PDA conditions 27 3.4 Post metallization annealing 31 Chapter 4: BTI characteristics of Si cap on Ge 36 4.1 Charge trapping measurements (CV-hysteresis) 36 4.1.1 Experimental procedure 36 4.1.2 Results and conclusion 38 4.1.3 Anomalous flat-band voltage shift 41 4.2 Stress-Induced Leakage Current (SILC) measurements 42 4.3 Hysteresis-stress time measurement 44 4.3.1 Introduction 44 4.3.2 Results and discussion 44 4.4 BTI measurements (CV-MSM) 45 4.4.1 Introduction 45 4.4.2 Experiments 46 4.4.3 Flat-band voltage shift and charge trapping 47 4.4.4 Results and discussion 48 4.5 C-V relaxation measurement 50 4.5.1 Introduction 50 4.5.2 Results and discussion 50 Chapter 5: Conclusion and outlook 52 References 54 | - |
| dc.language.iso | en | - |
| dc.title | 低溫成長矽鈍化層於氧化鉿/鍺金氧半之可靠性研究 | zh_TW |
| dc.title | Reliability of HfO2/Ge MOS with Si cap deposited at low temperatures | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 107-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.coadvisor | 郭瑞年 | zh_TW |
| dc.contributor.coadvisor | Raynien Kwo | en |
| dc.contributor.oralexamcommittee | 郭治群;安東尼奧茲 | zh_TW |
| dc.contributor.oralexamcommittee | Jyh-Chyurn Guo;Anthony Oates | en |
| dc.subject.keyword | 低溫成長矽鈍化層,鍺,高介電係數材料,電荷捕捉,可靠度分析, | zh_TW |
| dc.subject.keyword | low-temperature Si passivation,high-k dielectric materials,Germanium substrates,charge trapping,BTI reliability, | en |
| dc.relation.page | 58 | - |
| dc.identifier.doi | 10.6342/NTU201903467 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2019-08-16 | - |
| dc.contributor.author-college | 理學院 | - |
| dc.contributor.author-dept | 物理學系 | - |
| 顯示於系所單位： | 物理學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-107-2.pdf 目前未授權公開取用 | 3.83 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。