Skip navigation

DSpace JSPUI

DSpace preserves and enables easy and open access to all types of digital content including text, images, moving images, mpegs and data sets

Learn More
DSpace logo
English
中文
  • Browse
    • Communities
      & Collections
    • Publication Year
    • Author
    • Title
    • Subject
    • Advisor
  • Search TDR
  • Rights Q&A
    • My Page
    • Receive email
      updates
    • Edit Profile
  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77024
Title: 應用於穩定區塊鏈之隨機順序演算法硬體實現

Hardware Implementation of Random Sequential Algorithm Applied to Stable Blockchain
Authors: Yi-Ting Liu
柳亦廷
Advisor: 李致毅(CHIH-I LI)
Keyword: 隨機順序算法,加密演算法,FPGA 硬體設計實現,低功耗,動態調頻,
random sequential algorithm,encryption algorithm,FPGA hardware design and implementation,low power,dynamic reconfigure port,
Publication Year : 2020
Degree: 碩士
Abstract: 近年來,加密貨幣成為了不可忽視的一股新勢力,去中心化的設計、公開透明的交易紀錄、防竊且防偽造的算法機制……等優點。以比特幣為例,透過工作量證明(PoW)的方式來提供獎勵,既能提供穩定的加密算力也能獎勵提供算力者,由此來達成整個體制。
越大的算力,越能保障貨幣的安全性及穩定性。從最開始的CPU、GPU到FPGA、ASIC的進化過程,提供了最省能源但卻提供最大的算力來穩固加密貨幣的價值。若今日某方持有大量算力也就失去了去中心化的優點了,因此大家勢必都會使用ASIC鞏固加密貨幣。
本論文提出了一使用40奈米製程作為基準合成、優化演算法並且實現在FPGA的過程及結果,主要針對一種隨機順序的算法,這裡頭又包含了16種子算法,每種算法實現的難易度都有落差,因此在本論文中也著重在如何將各個算法調整達到最大效益,先以幾個較為難實現的算法作為基準下去做修改,同時也有在討論各種不同整合16種算法的架構。
在40奈米製程下合成結果頻率可以操作在200MHz,花費大約1500個週期就能完成一輪的計算,而實現在FPGA上則是操作在50MHz。最後也有討論兩種方式可以增加算力。

In recent years, cryptocurrency has become a new force that cannot be ignored, such as decentralized design, open and transparent transaction records, anti-theft and anti-counterfeiting mechanisms...etc. Taking Bitcoin as an example, rewards are provided through proof-of-work (PoW), which can provide stable hash rate, thereby achieving the entire system.
The greater the computing power, the better the security and stability of the currency. The evolution process from the initial CPU, GPU to FPGA, ASIC provides the most energy-saving but provides the most hash rate to stabilize the value of cryptocurrency. If a certain person holds a lot of hash rate today, it will lose the advantages of decentralization, so everyone is bound to use ASIC to consolidate cryptocurrency.
This paper proposes a process and results that use 40nm process as the benchmark for synthesis, optimization algorithm and implementation in FPGA. There are 16 algorithms in random sequential algorithm, and we also focus on how to adjust each algorithm to achieve the maximum benefit. First, we will use a few difficult algorithms as a benchmark to make changes. At the same time, we are discussing various different architectures that integrate 16 algorithms.
Under the 40nm process, the synthesized frequency can be operated at 200MHz, and it takes about 1500 cycles to complete a round of calculations, while the FPGA implementation is operated at 50MHz. In final, there are two ways to increase computing power.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77024
DOI: 10.6342/NTU202001700
Fulltext Rights: 未授權
Appears in Collections:電子工程學研究所

Files in This Item:
File SizeFormat 
U0001-2107202016263800.pdf
  Restricted Access
2.48 MBAdobe PDF
Show full item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

社群連結
聯絡資訊
10617臺北市大安區羅斯福路四段1號
No.1 Sec.4, Roosevelt Rd., Taipei, Taiwan, R.O.C. 106
Tel: (02)33662353
Email: ntuetds@ntu.edu.tw
意見箱
相關連結
館藏目錄
國內圖書館整合查詢 MetaCat
臺大學術典藏 NTU Scholars
臺大圖書館數位典藏館
本站聲明
© NTU Library All Rights Reserved