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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77024完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(CHIH-I LI) | |
| dc.contributor.author | Yi-Ting Liu | en |
| dc.contributor.author | 柳亦廷 | zh_TW |
| dc.date.accessioned | 2021-07-10T21:43:42Z | - |
| dc.date.available | 2021-07-10T21:43:42Z | - |
| dc.date.copyright | 2020-07-29 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-07-22 | |
| dc.identifier.citation | [1] Tron Black and Joel Weight, “X16R – ASIC Resistant by Design”, IEE Proceedings-F, Vol. 139, No. 5, Oct. 1992. [2] Bruce Fenton and Tron Black, “Ravencoin: A Peer to Peer Electronic System for the Creation and Transfer of Assets “, April 3. 2018 [3] Jean-Philippe Aumasson, “BLAKE2: simpler, smaller, fast as MD5 “, January 29. 2013 [4] Liliya Andreicheva, “Blue Midnight Wish “, May 12. 2010 [5] Danilo Gligoroski and Vlastimil Klima and Svein Johan Knapskog and Mohamed El-Hadedy and Jørn Amundsen and Stig Frode Mjølsnes, “Cryptographic Hash Function - BLUE MIDNIGHT WISH “, September. 2009 [6] Praveen Gauravaram and Lars R. Knudsen1 and Krystian Matusiewicz and Florian Mendel and Christian Rechberger and Martin Schl¨affer and and Søren S. Thomsen, “Grøstl – a SHA-3 candidate “, March 2. 2011 [7] E. Andreeva, C. Bouillaguet, P.-A. Fouque, J. J. Hoch, J. Kelsey, A. Shamir, and S. Zimmer. Second Preimage Attacks on Dithered Hash Functions. In N. Smart, editor, Advances in Cryptology – EUROCRYPT 2008, Proceedings, volume 4965 of Lecture Notes in Computer Science, pages 270–288. Springer, 2008. [8] Guido BERTONI and Joan DAEMEN and Michaael PEETERS and Gilles VAN ASSCHE, “The Keccak reference “, January 14. 2011 [9] Niels Ferguson and Stefan Lucks and Bruce Schneier and Doug Whiting and Mihir Bellare and Tadayoshi Kohno and Jon Callas and Jesse Walker, “The Skein Hash Function Family “, October 1. 2010 [10] Christophe De Canni`ere and Hisayoshi Sato, Dai Watanabe, “Hash Function Luffa “, October 31. 2008 [11] Ga¨etan Leurent, “SIMD Is a Message Digest “ [12] Eli Biham and Orr Dunkelman, “The SHAvite-3 Hash Function “, November 23.2009 [13] J.-P. Aumasson and W. Meier. Zero-sum distinguishers for reduced Keccak-f and for the core functions of Luffa and Hamsi. NIST mailing list, 2009 [14] Ryad Benadjila and Olivier Billet and Henri Gilbert and Gilles Macario-Rat and Thomas Peyrin and Matt Robshaw and Yannick Seurin, “SHA-3 Proposal: ECHO “, September 14.2009 [15] Ozgül Küçük, “The Hash Function Hamsi“, October 29, 2008 [16] Shai Halevi and William E. Hall and Charanjit S. Jutla, IBM T.J. Watson Research Center, “The Hash Function Fugue “, October 29, 2008 [17] Saphir project, “Shabal, a Submission to NIST’s Cryptographic Hash Algorithm Competition “, October 28, 2008 [18] Paulo S.L.M. Barreto and Vincent Rijmen, “The WHIRLPOOL Hashing Function “, May 24, 2003 [19] Shay Gueron and Simon Johnson and Jesse Walker, “SHA-512/256 “, October 28. 2008 [20] Itai Dinur and Adi Shamir, “An Improved Algebraic Attack on Hamsi-256” 2010 [21] Thomas Fuhr, “Finding Second Preimages of Short Messages for Hamsi-256” 2010 [22] Danilo Gligorosk, “Narrow-pipe SHA-3 candidates differ significantly from ideal random functions defined over big domains” 2010 [23] Jean-Philippe Aumasson, Emilia Käsper, Lars Ramkilde Knudsen, Krystian Matusiewicz, Rune Ødegaard, Thomas Peyrin and Martin Schläffer, “Distinguishers for the compression function and output transformation of Hamsi-256”, 2010 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77024 | - |
| dc.description.abstract | 近年來,加密貨幣成為了不可忽視的一股新勢力,去中心化的設計、公開透明的交易紀錄、防竊且防偽造的算法機制……等優點。以比特幣為例,透過工作量證明(PoW)的方式來提供獎勵,既能提供穩定的加密算力也能獎勵提供算力者,由此來達成整個體制。 越大的算力,越能保障貨幣的安全性及穩定性。從最開始的CPU、GPU到FPGA、ASIC的進化過程,提供了最省能源但卻提供最大的算力來穩固加密貨幣的價值。若今日某方持有大量算力也就失去了去中心化的優點了,因此大家勢必都會使用ASIC鞏固加密貨幣。 本論文提出了一使用40奈米製程作為基準合成、優化演算法並且實現在FPGA的過程及結果,主要針對一種隨機順序的算法,這裡頭又包含了16種子算法,每種算法實現的難易度都有落差,因此在本論文中也著重在如何將各個算法調整達到最大效益,先以幾個較為難實現的算法作為基準下去做修改,同時也有在討論各種不同整合16種算法的架構。 在40奈米製程下合成結果頻率可以操作在200MHz,花費大約1500個週期就能完成一輪的計算,而實現在FPGA上則是操作在50MHz。最後也有討論兩種方式可以增加算力。 | zh_TW |
| dc.description.abstract | In recent years, cryptocurrency has become a new force that cannot be ignored, such as decentralized design, open and transparent transaction records, anti-theft and anti-counterfeiting mechanisms...etc. Taking Bitcoin as an example, rewards are provided through proof-of-work (PoW), which can provide stable hash rate, thereby achieving the entire system. The greater the computing power, the better the security and stability of the currency. The evolution process from the initial CPU, GPU to FPGA, ASIC provides the most energy-saving but provides the most hash rate to stabilize the value of cryptocurrency. If a certain person holds a lot of hash rate today, it will lose the advantages of decentralization, so everyone is bound to use ASIC to consolidate cryptocurrency. This paper proposes a process and results that use 40nm process as the benchmark for synthesis, optimization algorithm and implementation in FPGA. There are 16 algorithms in random sequential algorithm, and we also focus on how to adjust each algorithm to achieve the maximum benefit. First, we will use a few difficult algorithms as a benchmark to make changes. At the same time, we are discussing various different architectures that integrate 16 algorithms. Under the 40nm process, the synthesized frequency can be operated at 200MHz, and it takes about 1500 cycles to complete a round of calculations, while the FPGA implementation is operated at 50MHz. In final, there are two ways to increase computing power. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-10T21:43:42Z (GMT). No. of bitstreams: 1 U0001-2107202016263800.pdf: 2536333 bytes, checksum: 8ad86b6d040fb0ba59b243af3e85dcaf (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 口試委員會審定書 # 中文摘要 i ABSTRACT ii CONTENTS iii LIST OF FIGURES v LIST OF TABLES viivii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 1 Chapter 2 Introduction of the Random Sequential Algorithm 3 2.1 Random Sequential Algorithm 3 2.2 Problem Discussion 5 Chapter 3 Circuit of Random Sequence Algorithm 8 3.1 Design Consideration 8 3.2 Basic Circuit 10 3.2.1 The Architecture of Basic Circuit 10 3.2.2 Implementation of Hamsi 11 3.2.3 Implementation of Simd 14 3.2.4 Implementation of Others 17 3.2.5 Power, Performance and Area 22 Chapter 4 Measurement Results 25 4.1 Configure Design on FPGA 25 4.2 Results of FPGA 26 Chapter 5 Future Work 31 5.1 Design Optimization 31 5.1.1 Pipeline Circuit 31 5.1.2 Highly Reusing Operator 34 5.2 Conclusions 35 REFERENCE 36 | |
| dc.language.iso | en | |
| dc.subject | 低功耗 | zh_TW |
| dc.subject | FPGA 硬體設計實現 | zh_TW |
| dc.subject | 隨機順序算法 | zh_TW |
| dc.subject | 加密演算法 | zh_TW |
| dc.subject | 動態調頻 | zh_TW |
| dc.subject | encryption algorithm | en |
| dc.subject | dynamic reconfigure port | en |
| dc.subject | low power | en |
| dc.subject | FPGA hardware design and implementation | en |
| dc.subject | random sequential algorithm | en |
| dc.title | 應用於穩定區塊鏈之隨機順序演算法硬體實現 | zh_TW |
| dc.title | Hardware Implementation of Random Sequential Algorithm Applied to Stable Blockchain | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 楊家驤(CHIA-HSIANG YANG),張迪鈞(TI-CHUN CHANG) | |
| dc.subject.keyword | 隨機順序算法,加密演算法,FPGA 硬體設計實現,低功耗,動態調頻, | zh_TW |
| dc.subject.keyword | random sequential algorithm,encryption algorithm,FPGA hardware design and implementation,low power,dynamic reconfigure port, | en |
| dc.relation.page | 38 | |
| dc.identifier.doi | 10.6342/NTU202001700 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2020-07-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位: | 電子工程學研究所 | |
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