用於睡眠階段辨識系統之低雜訊低功率腦波訊號讀取電路設計

Abstract

本論文提出了一個低雜訊低功率的腦波訊號讀取電路，此電路包含了低雜訊低功率放大器以及類比數位轉換器(ADC)。放大器的架構是選用電容式耦合儀表放大器主要是因為省電。數位類比轉換器的部分則是選用循序漸進式(SAR)類比數位轉換器(ADC)。在本設計中，藉由於類比數位轉換器在進行轉換時將前端放大器操作於睡眠模式，因此放大器的消耗功率能夠在系統層面上更進一步的降低。 此讀取電路使用0.18umCMOS製程製作，其所占的面積為0.68mm2。根據post-layoutsimulation的結果，整體系統在1.2V的操作電壓下，其消耗功率為313nW。放大器的輸入雜訊為1.378uVrmsNEF為2.66。數位類比轉換器的SNDR與SFDR分別是61dB與-77.5dBDNL與INL分別是-0.2/0.1與-0.5/0.1LSB。

This thesis presents a low-noise low-power EEG readout circuit including a low-noise low-power amplifier and an analog-to-digital converter (ADC). A capacitively-coupled instrumentation amplifier is employed as the front-end amplifier due to its low power consumption, and a successive approximation register (SAR) ADC is chosen as the quantization module. In this proposed design, the amplifier power can be reduced further in system level by operating the front-end amplifier in sleep mode when the SAR ADC performs conversion. This readout circuit is implemented in 0.18um CMOS process and occupies 0.68 mm2. According to the post-layout simulation results, the system power is 313nW at 1.2V supply. The amplifier input referred noise is 1.378uVrms and it achieves 2.66 of NEF. The ADC’s SNDR and SFDR are 61dB and -77.5dB, respectively, and its DNL and INL are -0.2/0.1 and -0.5/0.1 LSB, respectively.