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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉宗德(Tsung-Te Liu) | |
| dc.contributor.author | Chi-Hsun Wu | en |
| dc.contributor.author | 吳奇勳 | zh_TW |
| dc.date.accessioned | 2021-07-10T21:41:59Z | - |
| dc.date.available | 2021-07-10T21:41:59Z | - |
| dc.date.copyright | 2020-08-28 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-08-13 | |
| dc.identifier.citation | [1] X. Zou, X. Xu, L. Yao and Y. Lian, 'A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip,' IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1067-1077, April 2009. [2] J. Lee, K. Lee, U. Ha, J. Kim, K. Lee, S. Gweon, J. Jang and H. Yoo, 'A 0.8-V 82.9-uW In-Ear BCI Controller IC with 8.8 PEF EEG Instrumentation Amplifier and Wireless BAN Transceiver,' IEEE Journal of Solid-State Circuits, vol. 54, no. 4, pp. 1185-1195, April 2019. [3] S. Park, J. Cho, K. Na and E. Yoon, 'Modular 128-Channel Δ – ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems,' IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 501-514, Feb. 2018. [4] C. Liu, S. Chang, G. Huang and Y. Lin, 'A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,' IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [5] Q. Fan, F. Sebastiano, J. H. Huijsing and K. A. A. Makinwa, “A 1.8uW 60nV/√ Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes,' IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1534-1543, July 2011. [6] F. Zhang, J. Holleman and B. P. Otis, 'Design of Ultra-Low Power Biopotential Amplifiers for Biosignal Acquisition Applications,' IEEE Transactions on Biomedical Circuits and Systems, vol. 6, no. 4, pp. 344-355, Aug. 2012. [7] H. Chandrakumar and D. Marković, 'An 80-mVpp Linear-Input Range, 1.6-GΩ Input Impedance, Low-Power Chopper Amplifier for Closed-Loop Neural Recording That Is Tolerant to 650-mVpp Common-Mode Interference,' IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 2811-2828, Nov. 2017. [8] L. Shen, N. Lu and N. Sun, 'A 1V 0.25uW inverter-stacking amplifier with 1.07 noise efficiency factor,' 2017 Symposium on VLSI Circuits, pp. C140-C141. [9] Y. Chen, D. Blaauw and D. Sylvester, 'A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording,' 2014 Symposium on VLSI Circuits Digest of Technical Papers, pp. 1-2. [10] J. G. Webster, Medical instrumentation: application and design. New York: Wiley, 1998. [11] https://www.thenewslens.com/article/119923 [12] https://expertsleep.com/sleep-education/sleep-studies/ [13] https://choosemuse.com/muse-s/ [14] https://en.wikipedia.org/wiki/Electroencephalography [15] C. Tu and T. Lin, 'Measurement and parameter characterization of pseudo-resistor based CCIA for biomedical applications,' 2014 IEEE International Symposium on Bioelectronics and Bioinformatics, pp. 1-4. [16] F. M. Yaul and A. P. Chandrakasan, 'A Noise-Efficient 36nV/√Hz Chopper Amplifier Using an Inverter-Based 0.2-V Supply Input Stage,' IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 3032-3042, Nov. 2017. [17] A. M. Abo and P. R. Gray, 'A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,' IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999. [18] S. Jiang, M. A. Do, K. S. Yeo and W. M. Lim, 'An 8-bit 200-MSample/s Pipelined ADC with Mixed-Mode Front-End S/H Circuit,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1430-1440, July 2008. [19] R. R. Harrison and C. Charles, 'A low-power low-noise CMOS amplifier for neural recording applications,' IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp. 958-965, June 2003. [20] L. Zeng, B. Liu and C. Heng, 'A Dual-Loop Eight-Channel ECG Recording System with Fast Settling Mode for 12-Lead Applications,' IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 1895-1906, July 2019. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76971 | - |
| dc.description.abstract | 本論文提出了一個低雜訊低功率的腦波訊號讀取電路，此電路包含了低雜訊低功率放大器以及類比數位轉換器(ADC)。放大器的架構是選用電容式耦合儀表放大器主要是因為省電。數位類比轉換器的部分則是選用循序漸進式(SAR)類比數位轉換器(ADC)。在本設計中，藉由於類比數位轉換器在進行轉換時將前端放大器操作於睡眠模式，因此放大器的消耗功率能夠在系統層面上更進一步的降低。 此讀取電路使用0.18umCMOS製程製作，其所占的面積為0.68mm2。根據post-layoutsimulation的結果，整體系統在1.2V的操作電壓下，其消耗功率為313nW。放大器的輸入雜訊為1.378uVrmsNEF為2.66。數位類比轉換器的SNDR與SFDR分別是61dB與-77.5dBDNL與INL分別是-0.2/0.1與-0.5/0.1LSB。 | zh_TW |
| dc.description.abstract | This thesis presents a low-noise low-power EEG readout circuit including a low-noise low-power amplifier and an analog-to-digital converter (ADC). A capacitively-coupled instrumentation amplifier is employed as the front-end amplifier due to its low power consumption, and a successive approximation register (SAR) ADC is chosen as the quantization module. In this proposed design, the amplifier power can be reduced further in system level by operating the front-end amplifier in sleep mode when the SAR ADC performs conversion. This readout circuit is implemented in 0.18um CMOS process and occupies 0.68 mm2. According to the post-layout simulation results, the system power is 313nW at 1.2V supply. The amplifier input referred noise is 1.378uVrms and it achieves 2.66 of NEF. The ADC’s SNDR and SFDR are 61dB and -77.5dB, respectively, and its DNL and INL are -0.2/0.1 and -0.5/0.1 LSB, respectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-10T21:41:59Z (GMT). No. of bitstreams: 1 U0001-3007202018280500.pdf: 2614678 bytes, checksum: eec76acb90a195352f68543591e5ed36 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 口試委員會審定書 ............................................................................................................ I 誌謝 ................................................................................................................................... II 摘要 .................................................................................................................................. III ABSTRACT ........................................................................................................................ IV CHAPTER 1 INTRODUCTION .......................................................................................... 1 1.1 Motivation ...................................................................................................................... 1 1.2 Thesis Organization....................................................................................................... 2 CHAPTER 2 BIOMEDICAL SENSOR INTERFACE ............................................................. 3 2.1 Introduction ................................................................................................................... 3 2.2 Instrumentation Amplifiers (IAs) ................................................................................ 5 2.2.1 Capacitively-Coupled IA (CCIA) ...................................................................... 5 2.2.2 Capacitively-Coupled Chopper IA (Chopper CCIA) ...................................... 6 2.3 Analog-to-Digital Converter (ADC)............................................................................. 7 2.4 Summary ........................................................................................................................ 7 CHAPTER 3 CIRCUIT TECHNIQUES TO IMPROVE NOISE AND POWER EFFICIENCY .... 9 3.1 Capacitively-Coupled IA ............................................................................................... 9 3.2 Inverter Stacking Amplifier ....................................................................................... 11 3.3 Capacitively-Coupled Chopper IA............................................................................. 13 3.4 Multi-Chopper Amplifier ........................................................................................... 15 3.5 Mixed-Mode DC-Servo Loop ..................................................................................... 17 3.6 Summary ...................................................................................................................... 19 CHAPTER 4 PROPOSED DESIGN AND IMPLEMENTATION ............................................ 20 4.1 Introduction ................................................................................................................. 20 4.2 System Overview and Design Specification ............................................................... 21 4.3 Implementation ............................................................................................................ 23 4.3.1 Low-Noise Low-Power Front-End Amplifier ................................................. 23 4.3.2 Biasing Circuit and Sleep Mode Controller ................................................... 25 4.3.3 SAR ADC ........................................................................................................... 27 CHAPTER 5 MEASUREMENT RESULTS ........................................................................ 30 5.1 Low-Noise Low-Power Front-End Amplifier ........................................................... 31 5.2 SAR ADC ..................................................................................................................... 32 5.3 Sleep Mode Verification .............................................................................................. 33 5.4 Performance and Comparison ................................................................................... 36 CHAPTER 6 CONCLUSION AND FUTURE WORK .......................................................... 38 REFERENCE .................................................................................................................... 39 | |
| dc.language.iso | en | |
| dc.subject | 電容式耦合儀表放大器 | zh_TW |
| dc.subject | 低雜訊低功率放大器 | zh_TW |
| dc.subject | 生理訊號讀取電路 | zh_TW |
| dc.subject | 腦波訊號 | zh_TW |
| dc.subject | 前端放大器 | zh_TW |
| dc.subject | Front-end amplifier | en |
| dc.subject | Capacitively-coupled instrumentation amplifier | en |
| dc.subject | Low-Noise low-power amplifier | en |
| dc.subject | Biomedical readout circuit | en |
| dc.subject | EEG | en |
| dc.title | 用於睡眠階段辨識系統之低雜訊低功率腦波訊號讀取電路設計 | zh_TW |
| dc.title | A Low-Noise Low-Power EEG Readout Circuit for Sleep Staging Recognition System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),林宗賢(Tsung-Hsien Lin),李泰成(Tai-Cheng Lee) | |
| dc.subject.keyword | 腦波訊號,生理訊號讀取電路,前端放大器,低雜訊低功率放大器,電容式耦合儀表放大器, | zh_TW |
| dc.subject.keyword | EEG,Biomedical readout circuit,Front-end amplifier,Low-Noise low-power amplifier,Capacitively-coupled instrumentation amplifier, | en |
| dc.relation.page | 40 | |
| dc.identifier.doi | 10.6342/NTU202002124 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2020-08-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| U0001-3007202018280500.pdf 未授權公開取用 | 2.55 MB | Adobe PDF |
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