一個具混合架構參考電壓緩衝電路之十三位元連續漸進式類比至數位轉換器

Abstract

連續漸進式類比至數位轉換器以其在中高解析度可以有高電能效率而聞名，受惠於電容式數位至類比轉換器，其靜態耗能極低。然而，驅動該數位至類比轉換器並不容易，且其耗能遠遠多於連續漸進式類比至數位轉換器本身所消耗的。因此，混合架構參考電壓緩衝電路被引用，該電路包含一個動態的參考電壓穩壓器與電荷補償電路，可以迅速地調節參考電壓。參考電壓與連續漸進式類比至數位轉換器的性能高度相關。 本篇提出的作品，在奈奎斯特輸入頻率下，可以達到每秒五十萬次轉換頻率。作品的主動面積僅0.0277平方毫米，包含了混合架構參考電壓緩衝電路與連續漸進式類比至數位轉換器，且毋須外掛去耦電容。包含混合架構參考電壓緩衝電路的耗能，整體功耗為16.77微瓦特、品質因數達到165.3分貝。

The successive-approximation-register (SAR) analog-to-digital converter (ADC) is a well-known energy-efficient architecture for high intermediate resolution. Thanks to capacitive digital-to-analog converter (DAC), the static power consumption is extremely low. Nevertheless, driving of the DAC can be an effort, and its power consumption is much greater than SAR ADC’s. Hence, hybrid reference buffer circuit is introduced, and it comprises a dynamic reference voltage stabilizer (RVS) and charge compensation circuit, which can quickly regulate reference voltage (Vref). Vref is highly related with the performance of SAR ADC. This proposed work can achieve the conversion rate of 500 kS/s with Nyquist rate input frequency. Including hybrid reference buffer circuit and SAR ADC, the active area is only 0.0277 mm2 without external-decoupling capacitor. The power consumption is 16.77 μW and FoMS reaches 165.3 dB including hybrid reference buffer circuit.