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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Jyun-Chun Huang | en |
| dc.contributor.author | 黃竣淳 | zh_TW |
| dc.date.accessioned | 2021-06-17T09:07:15Z | - |
| dc.date.available | 2021-12-25 | |
| dc.date.copyright | 2019-12-25 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-12-06 | |
| dc.identifier.citation | [1] A. Vence, et al., “A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-∆∑ ADC with On-Chip Buffer in 28 nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 2951-2962, Aug. 2016.
[2] M. Liu, et al., “A 10-b 20-MS/s SAR ADC with DAC-Compensated Discrete-Time Reference Driver,” IEEE J. Solid-State Circuits, vol. 54, no. 2, pp. 417–427, Feb. 2019. [3] Y.-S. Hu, et al. “A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System,” IEEE J. Solid-State Circuits, vol. 54, no. 10, pp. 2680–2690, Oct. 2019. [4] M. Liu, et al., “A 0.8V 10b 80ks/S SAR ADC with Duty-Cycled Reference Generation,” in IEEE ISSCC Dig. Tech. Papers, pp. 278-279, Feb. 2015. [5] Y.-Z Lin, et al., “A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS,” in IEEE TCAS-I, vol. 60, no. 3, pp. 570-581, Mar. 2013. [6] C.-C. Lee, et al., “A SAR-Assisted Two-Stage Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 859-869, Apr. 2011. [7] H.-Y. Tai, et al., “A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 196–197, Feb. 2014. [8] Y.-S. Hu, et al. “A 510nW 12-bit 200kS/s SAR Assisted SAR ADC Using a Re-Switching Technique,” in Proc. IEEE Symp. VLSI Circuits, pp. C238–C239, Jun. 2017. [9] P. Harpe, et al., “A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data Driven Noise Reduction,” in IEEE ISSCC Dig. Tech. Papers, pp. 270-271, Feb. 2013. [10] J.-Y. Lin, et al., “A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC Utilizing a Redundancy-Facilitated Background Error-Detection-and-Correction Scheme,” in IEEE ISSCC Dig. Tech. Papers, pp. 458-459, Feb. 2015 [11] M.-H. Wu, et al., “A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC using Capacitor-Swapping Technique,” IEEE A-SSCC, pp. 157-159, Nov. 2012. [12] F. Van der goes, et al., “A 1.5mW 68dB SNDR 80MS/s 2× Interleaved SAR Assisted Pipelined ADC in 28nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 200- 201, Feb. 2014. [13] P. Harpe, et al., “An Oversampled 12/14b SAR ADC with Noise Reduction and Linearity Enhancements Achieving up to 79.1dB SNDR,” in IEEE ISSCC Dig. Tech. Papers, pp. 194-195, Feb. 2014. [14] C.-C. Liu, et al., “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [15] B. Ginsburg, et al., “500-MS/s 5-bit ADC in 65-nm CMOS with Split Capacitor Array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, April. 2007. [16] V. Hariprasath, et al., “Merged Capacitor Switching Based SAR ADC with Highest Switching Energy-Efficiency,” Electron. Lett., vol. 46, pp. 620-621, Apr. 2010. [17] C.-C. Liu, et al., “A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18μm CMOS,” in Proc. IEEE Symp. VLSI Circuits, pp. 241-242, Jun. 2010. [18] Y.-Z Lin, et al., “A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with Fast Reference Charge Neutralization and Background Timing-Skew Calibration in 16-nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, pp.C204-C205, Jun. 2016. [19] K.-H. Chen, “Power Management Techniques for Integrated Circuit Design,” pp. 85-93, Sep. 2016. [20] C.-H. Chan, et al., “60-dB SNDR 100-MS/s SAR ADCs with Threshold Reconfigurable Reference Error Calibration,” IEEE J. Solid-State Circuits, vol. 52, no. 10, pp. 2576-2588, Oct. 2017. [21] T. Morie, et al., “A 4.2mW 50MS/s 13bit CMOS SAR ADC with SNR and SFDR Enhancement Techniques,” IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, Jun. 2015. [22] A. M. Abo, et al., “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999. [23] M. Ho, et al., “A Low-Power Fast-Transient 90-nm Low-Dropout Regulator with Multiple Small-Gain Stages,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2466-2475, Nov. 2010. [24] M. V. Elzakker, et al., “A 10-Bit Charge Redistribution ADC Consuming 1.9μw at 1 MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [25] P. Harikumar et al., “Design of a Reference Voltage Buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS,” in Proc. IEEE Int. Symp. Circuits and System, pp. 249–252, May 2015. [26] S. Wei, et al., “An 11-bit 200MS/s Subrange SAR ADC with Charge-Compensation-Based Reference Buffer,” IEEE NEWCAS, Jun. 2016. [27] M. Inerfield, et al., “An 11.5-ENOB 100-MS/s 8mW Dual-Reference SAR ADC in 28nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, pp. 246–247, Jun. 2014. [28] Y.-S. Hu, et al., “An 89.55dB-SFDR 179.6dB-FoMs 12-bit l MS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration,” IEEE A-SSCC, pp. 253-256, Nov. 2018. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74770 | - |
| dc.description.abstract | 連續漸進式類比至數位轉換器以其在中高解析度可以有高電能效率而聞名，受惠於電容式數位至類比轉換器，其靜態耗能極低。然而，驅動該數位至類比轉換器並不容易，且其耗能遠遠多於連續漸進式類比至數位轉換器本身所消耗的。因此，混合架構參考電壓緩衝電路被引用，該電路包含一個動態的參考電壓穩壓器與電荷補償電路，可以迅速地調節參考電壓。參考電壓與連續漸進式類比至數位轉換器的性能高度相關。
本篇提出的作品，在奈奎斯特輸入頻率下，可以達到每秒五十萬次轉換頻率。作品的主動面積僅0.0277平方毫米，包含了混合架構參考電壓緩衝電路與連續漸進式類比至數位轉換器，且毋須外掛去耦電容。包含混合架構參考電壓緩衝電路的耗能，整體功耗為16.77微瓦特、品質因數達到165.3分貝。 | zh_TW |
| dc.description.abstract | The successive-approximation-register (SAR) analog-to-digital converter (ADC) is a well-known energy-efficient architecture for high intermediate resolution. Thanks to capacitive digital-to-analog converter (DAC), the static power consumption is extremely low. Nevertheless, driving of the DAC can be an effort, and its power consumption is much greater than SAR ADC’s. Hence, hybrid reference buffer circuit is introduced, and it comprises a dynamic reference voltage stabilizer (RVS) and charge compensation circuit, which can quickly regulate reference voltage (Vref). Vref is highly related with the performance of SAR ADC.
This proposed work can achieve the conversion rate of 500 kS/s with Nyquist rate input frequency. Including hybrid reference buffer circuit and SAR ADC, the active area is only 0.0277 mm2 without external-decoupling capacitor. The power consumption is 16.77 μW and FoMS reaches 165.3 dB including hybrid reference buffer circuit. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T09:07:15Z (GMT). No. of bitstreams: 1 ntu-108-R06943042-1.pdf: 4716756 bytes, checksum: b068ddbebc1fd16b3b3104ef4a442772 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II Abstract III Contents 1 List of Figures 3 List of Tables 6 Chapter 1 Introduction 7 1.1 Motivation 7 1.2 Thesis Organization 8 Chapter 2 Fundamentals of Analog-to-Digital Converter 9 2.1 Introduction 9 2.2 Static Performance 9 2.2.1 Offset and Gain Error 9 2.2.2 Differential and Integral Nonlinearity (DNL and INL) 10 2.3 Dynamic Performance 12 2.3.1 Signal-to-Quantization-Noise Ratio (SQNR) and Signal-to-Noise Ratio (SNR) 12 2.3.2 Total Harmonic Distortion (THD) 13 2.3.3 Spurious-Free Dynamic Range (SFDR) 13 2.3.4 Signal-to-Noise and Distortion Ratio (SNDR) 14 2.3.5 Effective Number of Bits (ENOB) 14 2.3.6 Figure of Merit (FoM) 14 2.4 Architectures of ADCs 16 2.4.1 Flash 16 2.4.2 Two-stage 17 2.4.3 Pipeline 18 2.4.4 Time-Interleaved (TI) 19 2.4.5 Successive-Approximation-Register (SAR) 20 2.5 Capacitive SAR ADC 22 2.5.1 KT/C Noise 22 2.5.2 Switching Method 23 Chapter 3 Hybrid Reference Buffer Circuit 29 3.1 Introduction 29 3.2 Switched Capacitor (SC) DC-DC Converter 29 3.2.1 Charge Pump and Charge Sharing Methods 31 3.3 Reference Voltage Stabilizer (RVS) in SAR ADC 33 3.3.1 Quiescent Current 34 3.3.2 Stability Analysis 36 3.3.3 Transient Response 38 3.3.4 Line Regulation and Load Regulation 40 3.3.5 Power Supply Rejection Ratio (PSRR) 42 3.3.6 Power Efficiency 42 Chapter 4 A 13-bit SAR ADC with Hybrid Reference Buffer Circuit 43 4.1 Introduction 43 4.2 Proposed Architecture 45 4.3 High Resolution SAR ADC Technique 52 4.3.1 Detect-and-Skip Algorithm and Re-Switching Technique 52 4.3.2 Aligned Switching Technique 55 4.3.3 Tracking Average 57 4.3.4 Bootstrapped Switch 58 4.3.5 Dynamic Comparator 59 4.4 Power Efficient Reference Buffer Circuit Technique 60 4.4.1 Accumulated Charge Compensation (ACC) 61 4.4.2 Multi-Gain Stage Dynamic Reference Voltage Stabilizer 65 4.4.3 Transient Response of RVS 76 4.4.4 Vcm Capacitor Reservoir 79 4.5 Summary 80 Chapter 5 Experimental Results 82 5.1 Measurement Setup 82 5.2 Measurement Results 84 Chapter 6 Conclusion and Future Work 94 6.1 Conclusion 94 6.2 Future Work 95 Bibliography 99 | |
| dc.language.iso | en | |
| dc.title | 一個具混合架構參考電壓緩衝電路之十三位元連續漸進式類比至數位轉換器 | zh_TW |
| dc.title | A 13-bit Successive-Approximation-Register Analog-to-Digital Converter with Hybrid Reference Buffer Circuit | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 鍾勇輝(Yung-Hui Chung),陳景然(Ching-Jan Chen),胡耀升(Yao-Sheng Hu) | |
| dc.subject.keyword | 連續漸進式,類比至數位轉換器,電壓穩壓器,電荷補償,電源系統, | zh_TW |
| dc.subject.keyword | successive-approximation register (SAR),analog-to-digital converter (ADC),voltage stabilizer,charge compensation,power system, | en |
| dc.relation.page | 103 | |
| dc.identifier.doi | 10.6342/NTU201904368 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-12-09 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-108-1.pdf 目前未授權公開取用 | 4.61 MB | Adobe PDF |
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