一個以雙迴路非同步控制之九十奈米十位元每秒取樣二億次的逐漸趨近式類比數位轉換器

Abstract

本論文提出一個應用於逐漸趨近式類比至數位轉換器的電路設計技術，並且基於所提出的技術，實現一個使用九十奈米製程的單通道十位元每秒取樣二億次的非同步逐漸趨近式類比至數位轉換器。該技術為雙迴路非同步控制，其大幅降低因傳統非同步控制架構的現在，在最低有效位元階段造成時間浪費的問題，提升操作速度。 本設計使用台積電 90-nm UTM CMOS製程來實作晶片，其核心的電路面積為 192 µm × 115 µm。佈局後模擬結果顯示，此設計在0.9伏特的電壓與每秒取樣二億取樣的操作速度下，總消耗功率為1.61 mW，有效位元數為9.26 bits，每次資料轉換所消耗的能量為13fJ。預估最大DNL與INL的一個標準差分別為0.298LSB與0.35 LSB。 本次設計已於2019/07/10下線，目前正在製作階段。排定於2019/09/26晶片製作完成

This thesis proposes a control architecture for successive-approximation (SAR) analog-to-digital converters (ADCs). A single-channel 10-bit 200-MS/s asynchronous SAR ADC in 90-nm CMOS process was realized based on the proposed architecture. The proposed architecture is a dual-loop asynchronous control scheme. It reduce the waste time problem in LSB steps, which result from the architectural limitation of a conventional asynchronous control. Therefore, increase the speed. The physical design was implement in TSMC 90-nm CMOS process. The core area is 115 µm × 192 µm. From post-layout simulation, at 0.9 V supply voltage and 200-MS/s sampling rate, the total power consumption is 1.61 mW, and ENOB is 9.26 bits. The prediction of maximum 1-sigma DNL and INL are 0.298 LSB and 0.35 LSB respectively This design is in fabrication process and was taped out at 2019/07/10。The chip out was scheduled to 2019/09/26.