可降低測試圖樣數目之平行化自動測試圖樣產生技術

Abstract

隨著積體電路設計尺寸和複雜性的不斷增長，對高質量測試集的需求也隨之出現。 但是，高質量的測試集的大小通常非常大，所以測試圖樣壓縮的方法變得非常重要。 在本論文中，我們提出了一種基於多線程系統的平行化自動圖樣產生技術。 所提出的ATPG可以提高壓縮效率以減少測試圖樣數目。而確定性也在本論文中被考慮。 本論文提出的方法在ISCAS89和ITC99測試電路上進行實驗，實驗結果顯示，所提出的技術在減少測試圖樣數目方面有2.7%~41%的改進，而不會犧牲故障覆蓋率及時間。

As VLSI designs continue to grow in size and complexity, the demand for high-quality test sets arises for testing. However, the size of the high-quality test set is usually very large so the method of test pattern compaction becomes very important. In this thesis, we proposed a parallel N-pattern compaction ATPG which is based on a multi-threading system. The proposed ATPG can improve the compaction efficiency to reduce the test pattern count. Determinism is also considered in our technique. The proposed techniques are validated using ISCAS89 (International Symposium on Circuits and Systems) and ITC99 benchmark circuits. The experimental results show that the proposed techniques have considerable improvement considerable improvement from 2.7% to 41% in reducing test pattern count without sacrificing fault coverage and run time.