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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎 | |
| dc.contributor.author | Bo-Yi Li | en |
| dc.contributor.author | 李柏毅 | zh_TW |
| dc.date.accessioned | 2021-06-17T04:25:00Z | - |
| dc.date.available | 2023-08-19 | |
| dc.date.copyright | 2018-08-19 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-08-15 | |
| dc.identifier.citation | [1] S.C. Ma, P. Franco, E.J. McCluskey. 'An experimental chip to evaluate test tech-niques: Experiment results.' In International Test Conference, 1995.
[2] J.T.Y. Chang, C.W Tseng, C.M.J. Li, M. Purtell, E.J. McCluskey. 'Analysis of pat-tern-dependent and timing-dependent failures in an experimental test chip.' In In-ternational Test Conference, 1998. [3] C.W. Tseng and E.J. McCluskey. “Multiple-Output Propagation Transition Fault Test,” In International Test Conference, 2001, pp. 358-366. [4] B. Benware, C. Schuermyer, N. Tamarapalli, K.H. Tsai, S. Ranganathan, R. Madge, J. Rajski, P. Krishnamurthy. 'Impact of multiple-detect test patterns on product quality.' In International Test Conference, 2003. [5] X. Lin, K. Tsai, C. Wang, M. Kassab, J. Rajaski, T. Kobayashi, R. Klingenberg, Y. Sato, S. Hamada, and T. Aikyo. “Timing-aware ATPG for high quality at-speed testing of small delay defects,” In Asian Test Symposium, Nov. 2006, pp.139-146. [6] P. Girard. 'Survey of low-power testing of VLSI circuits.' IEEE Design & test of computers, vol. 19.3, 2002, pp. 82-92. [7] M. Yilmaz, K. Chakrabarty, and M. Tehranipoor. “Test-pattern grading and pattern selection for small-delay defects,” In VLSI Test Symposium, Apr. 2008, pp. 233-239. [8] C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, B. Koenemann. 'OPMISR: the foundation for compressed ATPG vectors.' In International Test Conference, 2001. [9] N.A. Touba. 'Survey of test vector compression techniques.' IEEE Design & Test of Computers, vol. 23.4 ,2006, pp. 294-303. [10] J. P. Roth. 'Diagnosis of Automata Failures: A Calculus and a Method,' IBM jour-nal of Research and Development, vol. 10, July 1966, pp. 278-291. [11] P. Goel. 'An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,' IEEE Transactions on Computers, vol. C-30.3, Mar. 1981, pp. 215-222. [12] H. Fujiwara, and T. Shimono. 'On thle Acceleration of Test Generation Algo-rithms,' IEEE Transactions on Computers, vol. C-32.12, Dec. 1983, pp. 1137-1144. [13] I. Pomeranz, L.N. Reddy, S.M. Reddy. 'COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits.' In International Test Conference, 1991. [14] P.A. Krauss, M. Henftling. 'Efficient fault ordering for automatic test pattern gener-ation for sequential circuits.' In Asian Test Symposium, 1994. [15] A. Raghunathan, S.T. Chakradhar. 'Acceleration techniques for dynamic vector compaction.' In International Conference on Computer-Aided Design, 1995. [16] S. Remersaro, J. Rajski, S.M. Reddy, I. Pomeranz. 'A scalable method for the gen-eration of small test sets.' In Design, Automation and Test Conference in Europe, 2009. [17] Y. W. Chen and C.M. Li, 'Parallel Order Automatic Test Pattern Generation for Test Compaction,' In VLSI Test Symposium, 2018. [18] C.Y. Ku, H.M. Huang, Y. Z. Lin, and H.P. Wen. 'Suppressing Test Inflation in Shared-Memory Parallel Automatic Test Pattern Generation,' In Design Automa-tion Conference, 2014. [19] M.H. Schulz, E. Trischler, T.M. Sarfert. 'SOCRATES: A Highly Efficient Auto-matic Test Pattern Generation System,' IEEE Transactions on Computer-Aided Design, Jan. 1988, pp. 126-137. [20] M. Schulz and E. Auth. 'Advanced Automatic Test Pattern Generation and Re-dundancy Identificalion Techniques,' In Fault-Tolerant Computing Symposium, June 1988, pp. 30-35. [21] J. A. Waicukauski. 'ATPG fix Ultra-Large Structured Designs,' In International Test Conference, 1990, pp. 44-51. [22] K. Miyase, S. Kajihara, S.M. Reddy. “A Method of Static Test Compaction Based on Don’t Care Identification” In International Workshop on Electric Design, 2002 [23] S.B. Akers. 'On the role of independent fault sets in the generation of minimal test sets.' In International Test Conference, 1987. [24] I. Pomeranz, S.M. Reddy. 'The accidental detection index as a fault ordering heu-ristic for full-scan circuits.' In Design, Automation and Test Conference in Europe, 2005. [25] X. Cai, P. Wohl, J. A. Waicukauski, and P. Notiyath. “Highly efficient parallel ATPG based on shared memory.” In International Test Conference, November 2010. pp. 1-7. [26] R. Butler, B. Keller, R. Paliwalm, R. Schoonover and J. Swenton “Design and im-plementation of a parallel automatic test pattern generation algorithm with low test vector count.“ In International Test Conference, October 2000, pp. 530-537. [27] S. Patil and P. Banerjee, 'A Parallel Branch and Bound Algorithm for Test Genera-tion,' In Design Automation Conference, 1989, pp. 339-344. [28] S. J. Chandra and J. H. Patel. “Test generation in a parallel processing environment.” In International Test Conference, October 1988, pp. 11-14. [29] K.W. Yeh, J.L. Huang and L.T. Wang, 'CPP-ATPG: A Circular Pipeline Pro-cessing Based Deterministic Parallel Test Pattern Generator”, In International Test Conference, 2013 [30] C.H. Chang, K.W. Yeh and J.L. Huang, 'SDC-TPG: A Deterministic Ze-ro-Inflation Parallel Test Pattern Generator ' In Asian Test Symposium, 2015 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70266 | - |
| dc.description.abstract | 隨著積體電路設計尺寸和複雜性的不斷增長，對高質量測試集的需求也隨之出現。 但是，高質量的測試集的大小通常非常大，所以測試圖樣壓縮的方法變得非常重要。
在本論文中，我們提出了一種基於多線程系統的平行化自動圖樣產生技術。 所提出的ATPG可以提高壓縮效率以減少測試圖樣數目。而確定性也在本論文中被考慮。 本論文提出的方法在ISCAS89和ITC99測試電路上進行實驗，實驗結果顯示，所提出的技術在減少測試圖樣數目方面有2.7%~41%的改進，而不會犧牲故障覆蓋率及時間。 | zh_TW |
| dc.description.abstract | As VLSI designs continue to grow in size and complexity, the demand for high-quality test sets arises for testing. However, the size of the high-quality test set is usually very large so the method of test pattern compaction becomes very important.
In this thesis, we proposed a parallel N-pattern compaction ATPG which is based on a multi-threading system. The proposed ATPG can improve the compaction efficiency to reduce the test pattern count. Determinism is also considered in our technique. The proposed techniques are validated using ISCAS89 (International Symposium on Circuits and Systems) and ITC99 benchmark circuits. The experimental results show that the proposed techniques have considerable improvement considerable improvement from 2.7% to 41% in reducing test pattern count without sacrificing fault coverage and run time. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T04:25:00Z (GMT). No. of bitstreams: 1 ntu-107-R05943087-1.pdf: 1382013 bytes, checksum: 29abfc4be57788640727a8d5b1b4ef05 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Previous works and Preliminaries 3 2.1 Typical Serial ATPG 3 2.2 Test Compaction Technique 4 2.2.1 Dynamic Compaction 4 2.2.2 Static Compaction 5 2.2.3 Other Compaction Techniques 6 2.3 Parallel ATPG Techniques 6 2.3.1 Fault Partitioning 7 2.3.2 Search Space Partitioning 8 2.3.3 Heuristic Parallelization 9 2.3.4 Circuit Partitioning 10 2.4 Determinism Techniques 10 Chapter 3 Proposed Techniques 12 3.1 Overall Strategy Flow 12 3.2 Parallel ATPG with Master-and-Slave Structure 13 3.2.1 Implementation 13 3.2.2 Master Procedure 14 3.2.3 About Determinism 15 3.2.4 Merge Process 17 3.2.5 Slave Procedure 19 3.2.6 The Advantage Compared to Typical Dynamic Compaction 20 3.2.7 Backtrack Limit Issue 21 3.3 Comparison with the Proposed ATPG 23 3.3.1 Implementation 23 3.3.2 Procedure in Each Thread 23 3.3.3 About Determinism 24 3.3.4 Merge Process 25 3.3.5 The Disadvantage of the Method 26 Chapter 4 Experiment Result 27 4.1 Backtrack Limit Issue 27 4.2 Previous Works Setup 28 4.3 Comparison Between 3 Merge Methods 29 4.4 The Result of the Parallel ATPG with Master-and-Slave Structure 30 4.5 The Result of the Comparison Parallel ATPG 32 4.6 Comparison between Two Proposed Parallel ATPG 34 4.7 Pattern Count Result with Same Fault Coverage 35 4.8 About Determinism 36 Chapter 5 Conclusion 37 REFERENCE 38 | |
| dc.language.iso | en | |
| dc.subject | 測試圖樣壓縮 | zh_TW |
| dc.subject | 積體電路測試 | zh_TW |
| dc.subject | 自動測試圖樣產生技術 | zh_TW |
| dc.subject | 平行化 | zh_TW |
| dc.subject | 測試膨脹 | zh_TW |
| dc.subject | 確定性 | zh_TW |
| dc.subject | 多線程 | zh_TW |
| dc.subject | determinism | en |
| dc.subject | test pattern compaction | en |
| dc.subject | parallel | en |
| dc.subject | test inflation | en |
| dc.subject | multi-threading | en |
| dc.subject | VLSI testing | en |
| dc.subject | ATPG | en |
| dc.title | 可降低測試圖樣數目之平行化自動測試圖樣產生技術 | zh_TW |
| dc.title | Reducing Test Pattern Count by A Parallel N-pattern
Compaction ATPG | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 呂學坤,李進福,黃炫倫 | |
| dc.subject.keyword | 積體電路測試,自動測試圖樣產生技術,測試圖樣壓縮,平行化,測試膨脹,確定性,多線程, | zh_TW |
| dc.subject.keyword | VLSI testing,ATPG,test pattern compaction,parallel,test inflation,determinism,multi-threading, | en |
| dc.relation.page | 41 | |
| dc.identifier.doi | 10.6342/NTU201803400 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-107-1.pdf 未授權公開取用 | 1.35 MB | Adobe PDF |
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