第五代通訊系統關鍵元件之設計與研究

Abstract

本論文提出了三個第五代行動通訊的關鍵元件設計，其中包含了一低相位變化可變增益放大器、一超低方均根相位錯誤相移器以及一高速 I/Q 調變器。 在第二章，以 65 奈米金氧半場效電晶體製程實現之低相位變化和高增益控制範圍可變增益放大器是應用在 38 GHz 相位陣列系統。利用電流抽取(Currentsteering)與偏壓調整(Bias-adjusting)架構中相反的相位趨勢來達到相位的補償。另外，在輸出端採用偏壓調整的三疊接架構可以大幅增加增益控制範圍。此可變增益放大器在 32 dB 的增益控制範圍內僅有著 6.5°的相位變化。此外，在 52 mW 的功耗下，此電路可以在 33 到 48 GHz 的 3-dB 頻寬範圍內獲得 23.6 dB 的最大增益以及6.2 dBm 之 1dB 壓縮點輸出功率。 本文第三章描述且分析了一新穎相位補償技術利用數位控制人造介質傳輸線之超低方均根相位錯誤相移器。不同於其他毫米波被動相移器，此相移器包含了一向量產生器、一向量選擇器以及兩個數位控制人造介質傳輸線相移器以達到 22.5°相位解析度(4 位元)以及 360°全相位合成。在 36 到 40 GHz 中，量測結果之方均根相位誤差和增益誤差皆分別小於 2.6°以及 2.6 dB。在沒有任何功耗下，插入增益為-20.2 dB。藉由所提出之新穎相位補償技術，此相移器成功展現出很好的方均根相位錯誤表現。 最後，本文在第四章提出一 38 GHz 高速 I/Q 調變器實現在 90 奈米金氧半場效電晶體製程。藉由採用弱反轉區偏壓的改良式 Gilbert-cell 混頻器在 I/Q 路徑上，此調變器可以省下直流功耗以及所需的本地振盪源功率同時可以提供良好的增益表現。在 28.8 mW 直流功耗以及 0 dBm 本地振盪源功率下，量測結果可以提供-2±1 dB 的轉換增益。此外，為了達到高速傳輸，設計一精準四相位訊號產生器以降低 I/Q 的不平衡。此調變器在38 GHz可以展現出高於 35 dBc的鏡像抑制率並且在多個高階的正交振幅調變(QAM)實驗下驗證。

In this thesis, three key components of the fifth generation (5G) communication systems, including a low phase variation variable gain amplifier (VGA), an ultra-low RMS phase error phase shifter and a high-speed I/Q modulator are proposed. In chapter 2, a low phase variation and high gain control range VGA using 65-nm CMOS process is applied on a 38 GHz phased-array system. The phase compensation is achieved by combining the current-steering and bias-adjusting topologies due to their opposite trend of phase variation when tuning the gain. Moreover, the triple-cascode structure is adopted in the second stage with bias adjusting technique which can largely improve the gain control range. This VGA performs the phase variation of only 6.5°with over 32 dB gain control range. Besides, with 52 mW power consumption, this circuit can obtain the peak gain of 23.6 dB with the 3-dB bandwidth from 33 to 48 GHz and the OP1dB of 6.2 dBm. An ultra-low RMS phase error phase shifter with a novel phase compensation technique by using digital controlled artificial dielectric (DiCAD) transmission line is described and analyzed in Chapter 3. Unlike other passive phase shifters, this phase shifter consist of a vector generator, a vector selector and two DiCAD phase shifter cells to achieve 22.5° phase resolution (4-bit) and full 360° synthesizing. The measured RMS phase error and gain error are under 2.6 ̊ and 2.6 dB over 36 to 40 GHz, respectively. The average insertion gain is -20.2 dB with no dc consumption. With the proposed novel phase compensation technique, this phase shifter successfully demonstrate an outstanding performance on RMS phase error. Finally, a 38 GHz high-speed I/Q modulator fabricated in 90-nm CMOS is proposed in chapter 4. By adopting weak-inversion biasing modified Gilbert-cell mixers in I/Q paths, this modulator can save dc power consumption and LO power requirement while providing competitive gain performance simultaneously. The measured results show that it can provide -2±1 dB conversion gain with only 28.8 mW dc power and 0 dBm LO power. Besides, for high-speed transmission, a precise quadrature signal generator is designed to minimize the I/Q imbalance, this modulator can demonstrate better than -35 dBc image reject ratio (IRR) at 38 GHz and is verified by several high-level quadrature amplitude modulation (QAM) experiments.