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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64164
標題: | 具高能量效率之射頻發射器 Design of Energy-Efficient Wireless Transmitters |
作者: | Chun-Yu Lin 林君豫 |
指導教授: | 林宗賢 |
關鍵字: | 相位選擇器,半弦慮波器之OQPSK 調變,邊緣合併技術, Phase Selector,HS-OQPSK modulation,Edge-combining technique, |
出版年 : | 2012 |
學位: | 碩士 |
摘要: | 在無線傳輸系統中,低功耗以及高效能是主要的設計考量。本論文提出一可達到低功耗及高效能之調變架構。在傳統的以混波器為基底之發射機系統中,數位類比轉換器, 濾波器以及混波器會消耗大量的電流,並且會帶來許多類比電路的非理想效應。本調變系統的核心電路為一相位選擇器,用來取代上述電路以達到低功耗的效能,並且基於開路調變的特性,本系統可達到高傳輸效率的表現。
第一個作品為應用於二十四億赫茲之無線射頻發射器,使用相位切換之架構支援OQPSK, HS-OQPSK, 8-PSK,以及16-QAM之調變。本傳輸器實現於90奈米製程。量測結果顯示本傳輸系統在 -3 dBm的輸出功率下傳輸速度最高可達105 Mbps。其EVM值小於10.6 %,而在操作電壓為1.2伏特下消耗功耗為9.25毫瓦。第二個作品為第一個作品之改進版本,分別對嵌入式FIR濾波器所產生的數位突波以及16-QAM調變下的準確度做改進。 第三個作品為一應用於生醫系統之無線射頻發射器,使用邊緣合併以及相位切換之技術達到低功耗以及高傳輸速率。本晶片實現於0.18微米互補式金氧半製程,其效能於0.8伏特供應電壓下消耗330微瓦並達到15 Mps的傳輸資料量。 In the wireless communication system, low power and high efficiency are major concern, and this thesis proposes a modulation architecture which can achieve low power and high data rate requirement. For a traditional mixer-based transmitter architecture, the DACs, filters, and mixers consume large power under high data rate and induce many non-idealities of analog circuits. The core of the proposed modulation architecture is a phase selector, which replaces these analog circuits and achieves low-power performance. Furthermore, the open loop characteristic facilitates the high data rate operation. The first work is a 2.4-GHz wireless transmitter, which adopts phase selector technique and can support OQPSK, HS-OQPSK, 8-PSK, and 16-QAM modulation. This chip is fabricated in a 90-nm CMOS process. The experimental results show that the transmitter delivers 105-Mbps maximum data rate under -3 dBm output power. The EVM is lower than 10.6 %, and the total power consumption of the transmitter is 9.25 mW under a 1.2-V supply. The second work is improved from the first work. The improvement includes the FIR digital spur reducing and enhancing accuracy in 16-QAM modulation. The third work is for bio-medical wireless application. This work can achieve low power and high data rate by using edge combining and phase selector technique. This chip is fabricated in a 0.18-um CMOS process. The transmitter consumes 300 uW at 15 Mbps from a 0.8-V supply. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64164 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-101-1.pdf 目前未授權公開取用 | 5.85 MB | Adobe PDF |
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