保證快取同調的錯序執行方法用以快速並準確的模擬多核心系統晶片虛擬平台

Abstract

在積體電路設計流程的早期階段中，虛擬平台模擬是一個很常被使用的設計與驗證方法。但是隨著硬體的複雜度日趨增長，如何兼顧模擬效率和準度變成為了一個重要的課題。在這篇論文中，我們深入分析含快取同調的多核心系統晶片結構，並提出一個錯序執行的模擬方法來同時達成高模擬效率和時脈精準的模擬結果。這個方法包含了一個快取同調導向的同步管理機制以保證模組間溝通順序及內容的正確性，和一個由模擬蹤跡重組出系統時序的技術以重現模擬結果的時間準確度。從實驗結果中顯示，相較於傳統以時脈為單位正序執行的模擬方法，這個方法可以達到3倍以上的模擬速度，同時保證模擬結果可以達到時脈精準。

Virtual platform simulation is a widely adopted technique for early stages of hardware design and verifications. However, as the complexity of hardware system design grows, how to reserve both decent simulation efficiency and accuracy becomes an issue. In this thesis, we analyze the architecture of multi-processor system-on-chips (MPSoCs) with cache coherency, and propose an out-of-order simulation scheme to achieve both high performance and cycle-accurate results. The method includes a cache-coherency-oriented synchronization mechanism to ensure the correctness of inter-module communications, and a trace-driven timing reconstruction technique to restore timing accuracy. The experiment results show that the simulation speed outperforms the conventional in-order simulation scheme by more than 3 times, while the simulation results are shown to be cycle-accurate.