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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62796完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚(Chung-Yang (ric) | |
| dc.contributor.author | Hsin-Cheng Lin | en |
| dc.contributor.author | 林鑫成 | zh_TW |
| dc.date.accessioned | 2021-06-16T16:10:41Z | - |
| dc.date.available | 2013-03-15 | |
| dc.date.copyright | 2013-03-15 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-02-20 | |
| dc.identifier.citation | [1] George S. Fishman, “Discrete-Event Simulation: Modeling, Programming, and Analysis,” Springer, 2001.
[2] “IEEE Standard for Standard SystemC Language Reference Manual,” IEEE Std 1666-2011, 2012. [3] E. Viaud, F. Pecheux, A. Greiner, “An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles,” in Proc. of Design Automation and Test in Europe (DATE), pp. 94-99, March 2006. [4] L. Cai and D. Gajski, “Transaction Level Modeling: An Overview,” in Proc. IEEE International Conference on Hardware/Software Co-design & System Synthesis, pp.19-24, October 2003. [5] Kuen-Huei Lin, Siao-Jie Cai, Chung-Yang (Ric) Huang, “Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling,” in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 143-148, Jan. 2010. [6] Yu-Fu Yeh, Chung-Yang (Ric) Huang, Chi-An Wu, Hsin-Cheng Lin, “Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method,” in Proc. of Design, Automation & Test in Europe Conference (DATE), pp. 353-358, March 2011. [7] J. J. Pieper et al., “High Level Cache Simulation for Heterogeneous Multiprocessors,” in Proc. of Design Automation Conference (DAC), pp. 287-292, June 2004. [8] C.-Y. Fu, M.-H. Wu, and R.-S. Tsay, “A Shared-Variable-Based Synchronization Approach to Efficient Cache Coherence Simulation for Multi-Core Systems,” in Proc. of Design, Automation & Test in Europe Conference (DATE), pp. 347-352, March 2011. [9] D. Kim et al., “Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs,” in Proc. of International Symposium on System Synthesis (ISSS), pp. 174-179, June 2002. [10] D. Kim, Y. Yi, and S. Ha, “Trace-Driven HW/SW Cosimulation Using Virtual Synchronization Technique,” in Proc. of Design Automation Conference (DAC), pp. 345-348, July 2005. [11] M.-H. Wu, C.-Y. Fu, P.-C. Wang, and R.-S. Tsay, 'A High-Parallelism Distributed Scheduling Mechanism for Multi-Core Instruction-Set Simulation', in Proc. ACM International Conference on Embedded Software (EMSOFT), pp. 197-204, Nov. 2009. [12] Per Stenstrom, “A Survey of Cache Coherence Schemes for Multiprocessors,” IEEE Computer, vol. 23, pp.12-24, June 1990. [13] M. S. Papamarcos and J. H. Patel, “A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories,” in Proc. of the International Symposium on Computer Architecture (ISCA), pp. 348-354, June 1984. [14] “ARMv5 Architecture Reference Manual,” http://infocenter.arm.com. [15] G. Goumas et al., “Understanding the Performance of Sparse Matrix-Vector Multiplication,” in Proc. of Euromicro Conference on Parallel, Distributed and Network-based Processing, pp. 283-292, Feb. 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62796 | - |
| dc.description.abstract | 在積體電路設計流程的早期階段中，虛擬平台模擬是一個很常被使用的設計與驗證方法。但是隨著硬體的複雜度日趨增長，如何兼顧模擬效率和準度變成為了一個重要的課題。在這篇論文中，我們深入分析含快取同調的多核心系統晶片結構，並提出一個錯序執行的模擬方法來同時達成高模擬效率和時脈精準的模擬結果。這個方法包含了一個快取同調導向的同步管理機制以保證模組間溝通順序及內容的正確性，和一個由模擬蹤跡重組出系統時序的技術以重現模擬結果的時間準確度。從實驗結果中顯示，相較於傳統以時脈為單位正序執行的模擬方法，這個方法可以達到3倍以上的模擬速度，同時保證模擬結果可以達到時脈精準。 | zh_TW |
| dc.description.abstract | Virtual platform simulation is a widely adopted technique for early stages of hardware design and verifications. However, as the complexity of hardware system design grows, how to reserve both decent simulation efficiency and accuracy becomes an issue. In this thesis, we analyze the architecture of multi-processor system-on-chips (MPSoCs) with cache coherency, and propose an out-of-order simulation scheme to achieve both high performance and cycle-accurate results. The method includes a cache-coherency-oriented synchronization mechanism to ensure the correctness of inter-module communications, and a trace-driven timing reconstruction technique to restore timing accuracy. The experiment results show that the simulation speed outperforms the conventional in-order simulation scheme by more than 3 times, while the simulation results are shown to be cycle-accurate. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T16:10:41Z (GMT). No. of bitstreams: 1 ntu-102-R99921032-1.pdf: 603059 bytes, checksum: 18c81ddec335d516c7252c858240616c (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES viii LIST OF TABLES ix Chapter 1 Introduction 1 1.1 Efficiency and Accuracy Issues of Virtual Platform Based Design Methodology 1 1.2 Related Work 2 1.2.1 Conventional In-Order Simulation 2 1.2.2 TLM/T Modeling Method 2 1.2.3 Data-Dependency-Aware Synchronization and Scheduling Methods 3 1.2.4 Methods for Multi-Processor Cache Simulation 4 1.3 Contribution 5 1.4 Thesis Organization 5 Chapter 2 Out-of-order Simulation 7 2.1 The Importance of Simulation Scheduling 7 2.2 Discrete-Event Simulation 8 2.3 In-order Simulation Scheduling 9 2.4 Out-of-order Simulation Scheduling 11 Chapter 3 Cache Coherence Protocols 15 3.1 Types of Cache Coherence Protocols 16 3.2 The MESI Protocol 17 3.2.1 Cache States 17 3.2.2 Read Operation 18 3.2.3 Write Operation 20 3.2.4 Cache Flush 20 3.2.5 State Transitions 21 3.3 Simulation Challenges 22 Chapter 4 Cache-Coherency-Oriented Synchronization Mechanism 25 4.1 Essentials in System Simulation Correctness 25 4.2 Data-Dependency Checking Techniques 27 4.3 The Ultra Synchronization Checking Method (USCM) 28 4.3.1 Hardware-Based Static Data-Dependency Table 28 4.3.2 Hardware-Based Dynamic Data-Dependency Table 29 4.3.3 Software-Based Static Data-Dependency Table 29 4.3.4 Simulation Flow 30 4.4 Cache-Oriented Synchronization Technique 32 4.4.1 Observations on Cache Coherency Operations 32 4.4.2 Coherency Request Function 33 4.4.3 Example Revisited 35 4.4.4 Conclusion 37 Chapter 5 Timing Reconstruction 38 5.1 Timing Accuracy Concerns 38 5.1.1 Access latency 38 5.1.2 Resource Contention 39 5.2 Trace-Driven Timing Reconstruction 39 5.2.1 Access Traces 39 5.2.2 Trace Merging 41 5.2.3 Time Calculation 43 5.2.4 Timing Reconstruction Flow 44 5.3 Simulation Flow 47 Chapter 6 Implementations 49 6.1 Overview of Simulation Framework 49 6.1.1 SystemC Kernel 50 6.1.2 Hardware Processes 50 6.1.3 Simulation Engine 51 6.2 Controlling Flow 51 Chapter 7 Experiments 53 7.1 Experimental Setups 53 7.1.1 System Specification 53 7.1.2 Embedded Software Test Cases 54 7.1.3 Experimental Environment 56 7.2 Experimental Results 57 7.2.1 Case 1: FFT 57 7.2.2 Case 2: Sparse Matrix Multiplication 59 Chapter 8 Conclusions 60 REFERENCE 61 | |
| dc.language.iso | en | |
| dc.subject | 多核心系統晶片 | zh_TW |
| dc.subject | 蹤跡模擬時間重組 | zh_TW |
| dc.subject | 同步機制 | zh_TW |
| dc.subject | 快取同調性 | zh_TW |
| dc.subject | 錯序模擬 | zh_TW |
| dc.subject | 虛擬平台 | zh_TW |
| dc.subject | virtual platform | en |
| dc.subject | out-of-order simulation | en |
| dc.subject | cache-coherency | en |
| dc.subject | MPSoC | en |
| dc.subject | synchronization mechanism | en |
| dc.subject | trace-driven timing reconstruction | en |
| dc.title | 保證快取同調的錯序執行方法用以快速並準確的模擬多核心系統晶片虛擬平台 | zh_TW |
| dc.title | Cache-Coherence-Ensured Techniques for Fast and Accurate Out-of-Order MPSoC Virtual Platform Simulation | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王勝德(Sheng-De Wang),楊佳玲(Chia-Lin Yang),陳正堅(Ken Chen) | |
| dc.subject.keyword | 多核心系統晶片,虛擬平台,錯序模擬,快取同調性,同步機制,蹤跡模擬時間重組, | zh_TW |
| dc.subject.keyword | MPSoC,virtual platform,out-of-order simulation,cache-coherency,synchronization mechanism,trace-driven timing reconstruction, | en |
| dc.relation.page | 62 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-02-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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