利用錯誤更正快取以最佳化快閃記憶體組成之固態硬碟

Abstract

隨著製程技術的進步和多層式儲存(multi level cell, MLC)的使用，NAND型快閃記憶體的可信賴性持續退化。因此數個研究提倡採用一先進的錯誤更正碼技術-低密度奇偶檢查碼(low-density parity check code, LDPC code)。 低密度奇偶檢查碼可以藉由軟判決感測(soft-decision sensing)和軟判決解碼(soft-decision decoding)來提供高錯誤修復強度但卻會造成較長的讀取延遲。低密度奇偶檢查碼解碼器所需的軟判決感測和軟判決解碼迭代次數決定於低密度奇偶檢查碼所需要處理的錯誤量。在本篇論文中，我們提出一種新的設計概念以最佳化採用低密度奇偶檢查碼解碼器之NAND 型快閃記憶體固態硬碟。我們利用NAND型快閃記憶體在讀取相同頁時，錯誤位置會大部分相同之特性設計錯誤更正快取，用來快取已發現錯誤位元的正確資料。藉由事先修補快閃記憶體頁的資料來減少錯誤的位元量，加速之後的低密度奇偶檢查碼解碼程序。 為了研究我們提出的設計概念，我們建立了一分析快閃記憶體特性的工具、一低密度奇偶檢查碼模擬器和一固態硬碟模擬器。此外，我們為了探討錯誤更正快取的可能性和效力做了特性分析與評估。

With the advance of scaling memory technology and the adoption of MLC, the reliability of NAND flash memory continues to degrade. Therefore, several studies advocate adopting LDPC, an advanced ECC technique. LDPC can provide high error correction strength stemming from its soft-decision sensing and soft-decision decoding operations which result in longer read latency. The number of soft-decision sensing and soft-decision decoding iterations required by a LDPC decoder depends on the number of errors the LDPC need to deal with. In this thesis, we propose a new design concept for optimizing NAND flash based SSDs adopting LDPC decoders. We exploit the characteristic that the positions of errors are largely identical between reads to the same NAND flash page. We design ECC Cache to cache the correct data of flash bits that are found erroneous. By performing the patch of the raw NAND flash data in advance, the number of erroneous bits in the data is reduced and the latency of the following LDPC decoding procedure gains speedup. We build up a flash characterization tool, a LDPC simulator, and a SSD simulator, for studying the proposed concepts. Furthermore, we perform characterization and evaluation to explore the opportunities and effectiveness of ECC Cache.