藉由干擾緩解、修復和編程技術以強化快閃記憶體儲存系統的可靠度

Abstract

過去幾年來，記憶體製造商持續地尋求增加快閃記憶體的密度以滿足對於儲存系統空間持續成長的需求。先進的製程微縮、多階式儲存技術、以及三維架構都是非常流行的方法來進一步地增加晶片的空間以及降低位元的成本。同時，它們也引起嚴重的可靠度問題，例如: 逐漸惡化的寫入干擾、更短的耐久度、以及更高的錯誤率。為了解決干擾問題，我們提出了一套干擾減緩方案來減緩寫入干擾所造成的負面效果，特別針對同一區塊內的干擾。尤其，此方案藉由分散不可避免的干擾錯誤到無效資料的快閃記憶體空間上來降低資料錯誤率，並考慮到三維快閃記憶體的實體架構。為了解決耐久度問題，我們基於自我修復的科技提出了平均修復設計來平均地分散每個區塊上的修復次數。平均修復的目標在於延長快閃記憶體的壽命而不會引起大量的有效資料搬移。為了解決高錯誤率的問題，一個類單階式寫入策略被提出來更有效地利用臨界電壓關係來表示多階式位元資訊，進而大大地提供一個更大的臨界電壓的可用範圍，接近於在單階式晶片上所觀察到的。此策略不但可以有效地減少潛在的錯誤率並可以改善晶片的存取效能。

Over the past years, memory manufacturers are constantly seeking to increase flash memory density in order to fulfill the ever growing demand for storage capacity. Advanced process shrinking, Multi-Level-Cell technique, and even three dimension architecture are very popular approaches to further increase the chip capacity, as well as reduce the bit cost. At the same time, they also bring about serious reliability problems, e.g., deteriorated program disturbance, shorter endurance, and higher bit error rate (BER). To address the disturbance problem, we propose a emph{disturb-alleviation scheme} that can alleviate the negative effects caused by program disturb, especially inside a block. In particular, the scheme reduces the data error rate by distributing unavoidable disturbance errors over the flash-memory space of invalid data, with the considerations of the physical organization of 3D flash memory. To address the endurance problem, we propose emph{a heal-leveling design} that evenly distributes healing cycles to flash blocks based on the self-healing technology. The objective of heal-leveling is to extend the lifetime of flash memory without introducing a large amount of live-data copying overheads. To address the high BER problem, a emph{SLC-like programming strategy} is proposed to better exploit the threshold-voltage relationship to denote different Multi-Level-Cell bit information, which in turn drastically provides a larger available range of threshold voltage similar to that found in Single-Level-Cell chips. It could not only significantly reduce the potential bit error rate but also improve the access performance of chips.