一個十位元每秒3.2億次轉換操作於0.9V的連續漸進式類比至數位轉換器

Abstract

在無線高速傳收通訊系統中，需要中高解析度(8 to 10 bits)且每秒取樣幾億次的類比至數位轉換器(Analog-to-Digital Converter, ADC)來置於接收器端來處理從傳送器端傳來的訊號，然後再給後級的DSP晶片處理。在各種不同的架構中，連續漸進式式類比數位轉換器不需要放大器且內部架構大部分都是數位電路，因此可以達到高速與低功率運作的要求。 本論文主要提出的是一個十位元每秒3.2億次轉換操作於0.9伏特的單通道連續漸進式類比至數位轉換器，利用舒緩電容陣列穩定時間的技巧來改進電路整體時間的安排，搭配雙重參考電壓的方式降低整體電容陣列的大小，以解決高解析度類比至數位轉換器的速度瓶頸，如此不需額外的校正電路就可以達到高速低功耗的效果。在輸入頻率為奈奎斯特頻率下，主電路面積只有0.005184mm2，目前的量測結果為7.55的有效位元，功耗為0.673毫瓦，FoM為11.96fJ/conversion-step，SNDR、SFDR等動態的表現分別為47.18dB、67.7dB。靜態特性達到+8.21/-1 LSB的DNL與+2.75/-8.57 LSB的INL，以及1fF的小單位電容。

Several hundreds of MS/s analog-to-digital Converters (ADC) with 8 to 10 bits medium-to-high resolution are needed in high-speed wireless communication system, which is placed on the receiver to address the signal from the transceiver and then deliver to the DSP system in next stage. In different kinds of architectures, successive-approximation register (SAR) ADC can achieve the demands of high speed and low power because of not requiring opamp and most of its blocks are digital. This thesis proposes a 10-bit 320MS/s single-channel SAR ADC in 0.9V supply voltage. It uses a settling-time relief technique to extend the allocated DAC settling time and scales down the capacitor array with dual reference technique to resolve the speed bottleneck of high-resolution ADC. This SAR ADC does not need additional calibration to achieve low power dissipation and high speed operation. Without additional calibration circuit, the core circuit area is only 0.005184mm2. In the current measurement results with Nyquist rate input, its power consumption 0.673mW and gets 7.55 bits ENOB performance. As a result, the FoM performance is 11.96fJ/conversion-step. The dynamic performance parameters like SNDR and SFDR are 47.18dB and 67.7dB, respectively. Moreover, the static performance parameters of differential nonlinearity (DNL) and integral nonlinearity (INL) are +4.11/-1 LSB and +2.75/-8.57 LSB, respectively. The value of unit capacitor is only 1fF.