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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
dc.contributor.author | Chi-Huai Shih | en |
dc.contributor.author | 施紀懷 | zh_TW |
dc.date.accessioned | 2021-06-15T16:10:06Z | - |
dc.date.available | 2020-08-25 | |
dc.date.copyright | 2015-08-25 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-18 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/52239 | - |
dc.description.abstract | 在無線高速傳收通訊系統中,需要中高解析度(8 to 10 bits)且每秒取樣幾億次的類比至數位轉換器(Analog-to-Digital Converter, ADC)來置於接收器端來處理從傳送器端傳來的訊號,然後再給後級的DSP晶片處理。在各種不同的架構中,連續漸進式式類比數位轉換器不需要放大器且內部架構大部分都是數位電路,因此可以達到高速與低功率運作的要求。 本論文主要提出的是一個十位元每秒3.2億次轉換操作於0.9伏特的單通道連續漸進式類比至數位轉換器,利用舒緩電容陣列穩定時間的技巧來改進電路整體時間的安排,搭配雙重參考電壓的方式降低整體電容陣列的大小,以解決高解析度類比至數位轉換器的速度瓶頸,如此不需額外的校正電路就可以達到高速低功耗的效果。在輸入頻率為奈奎斯特頻率下,主電路面積只有0.005184mm2,目前的量測結果為7.55的有效位元,功耗為0.673毫瓦,FoM為11.96fJ/conversion-step,SNDR、SFDR等動態的表現分別為47.18dB、67.7dB。靜態特性達到+8.21/-1 LSB的DNL與+2.75/-8.57 LSB的INL,以及1fF的小單位電容。 | zh_TW |
dc.description.abstract | Several hundreds of MS/s analog-to-digital Converters (ADC) with 8 to 10 bits medium-to-high resolution are needed in high-speed wireless communication system, which is placed on the receiver to address the signal from the transceiver and then deliver to the DSP system in next stage. In different kinds of architectures, successive-approximation register (SAR) ADC can achieve the demands of high speed and low power because of not requiring opamp and most of its blocks are digital. This thesis proposes a 10-bit 320MS/s single-channel SAR ADC in 0.9V supply voltage. It uses a settling-time relief technique to extend the allocated DAC settling time and scales down the capacitor array with dual reference technique to resolve the speed bottleneck of high-resolution ADC. This SAR ADC does not need additional calibration to achieve low power dissipation and high speed operation. Without additional calibration circuit, the core circuit area is only 0.005184mm2. In the current measurement results with Nyquist rate input, its power consumption 0.673mW and gets 7.55 bits ENOB performance. As a result, the FoM performance is 11.96fJ/conversion-step. The dynamic performance parameters like SNDR and SFDR are 47.18dB and 67.7dB, respectively. Moreover, the static performance parameters of differential nonlinearity (DNL) and integral nonlinearity (INL) are +4.11/-1 LSB and +2.75/-8.57 LSB, respectively. The value of unit capacitor is only 1fF. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T16:10:06Z (GMT). No. of bitstreams: 1 ntu-104-R01943025-1.pdf: 2459417 bytes, checksum: 41b3ac916dee9cbe29a300c16c2e657c (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 致謝 I 摘要 II ABSTRACT III TABLE OF CONTENTS IV LIST OF FIGURES VII LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Thesis Organization 2 CHAPTER 2 FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTER 3 2.1 Introduction 3 2.2 Performance Metrics 3 2.2.1 Offset and Gain Error 3 2.2.2 Differential and Integral Nonlinearity (DNL, and INL) 4 2.2.3 Signal-to-Noise Ratio (SNR) 6 2.2.4 Total Harmonic Distortion (THD) 7 2.2.5 Spurious-Free Dynamic Range (SFDR) 7 2.2.6 Signal-to-Noise and Distortion Ratio (SNDR) 8 2.2.7 Effective Number of Bits (ENOB) 8 2.2.8 Figure of Merit (FoM) 8 2.3 Architecture of Analog to Digital Converter 9 2.3.1 Flash ADC Architecture 10 2.3.2 Two-Step and Subranging ADC Architecture 11 2.3.3 Pipeline ADC Architecture 13 2.3.4 Successive-Approximation Register ADC Architecture 15 CHAPTER 3 HIGH-SPEED LOW-POWER DESIGN CONSIDERATION 17 3.1 Introduction 17 3.1.1 The Conventional Asynchronous SAR ADC 17 3.1.2 The Speed Bottleneck of SAR ADC 18 3.2 Capacitive-DAC Design 19 3.2.1 Unit Capacitor Size 20 3.2.2 Switching Methods with Average Switching Energy 21 3.2.3 Settling Time 26 3.2.4 KT/C Noise 28 3.3 Comparator 31 3.3.1 Comparison Time 32 3.3.2 Input-Referred Noise 34 3.3.3 Kickback Noise 35 3.3.4 Offset Voltage 37 3.4 Summary 39 CHAPTER 4 PROPOSED ARCHITECTURE AND CIRCUIT IMPLEMENTATION 40 4.1 Introduction 40 4.2 Proposed Architecture 42 4.3 Proposed Capacitor Switching Method and Technique 44 4.3.1 Switchback Switching Method 44 4.3.2 Dual Reference Technique 47 4.4 Error Correction 49 4.5 Circuit Implementation 50 4.5.1 Bootstrap Circuit 50 4.5.2 Comparator 51 4.5.3 SA Control Logic (Digital Circuit ) 58 4.6 Overall ADC Simulation Results 60 4.6.1 Algorithm Simulation 60 4.6.2 Transistor Level Simulation 63 CHAPTER 5 CHIP SETUP AND MEASUREMENT RESULTS 65 5.1 Introduction 65 5.2 Chip Setup 65 5.2.1 Chip Layout Introduction 65 5.2.2 Measurement Instrument 67 5.2.3 PCB design 69 5.3 Measurement Results 74 5.3.1 Static Performance 75 5.3.2 Dynamic Performance 76 5.3.3 Power Dissipation 78 5.4 Summary 79 CHAPTER 6 CONCLUSION 81 BIBLIOGRAPHY 83 | |
dc.language.iso | en | |
dc.title | 一個十位元每秒3.2億次轉換操作於0.9V的連續漸進式類比至數位轉換器 | zh_TW |
dc.title | A 10-bit 320MS/s 0.9V SAR ADC | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),蔡宗亨(Tsung-Heng Tsai) | |
dc.subject.keyword | 連續漸進式類比至數位轉換器,高解析度,高速,低功率,小面積, | zh_TW |
dc.subject.keyword | SAR ADC,high resolution,high speed,low power,small area, | en |
dc.relation.page | 87 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-08-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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