一個使用迴路濾波器及驅動延遲磁滯控制的D類音頻放大器

Abstract

本篇論文提出了一個較簡單的磁滯控制D類音頻放大器(class D audio amplifier, CDA)電路實現。此電路實現在D類音頻放大器的輸出級之前加上了額外的時間延遲來達到磁滯控制的功能，因此我們將此種控制稱做驅動延遲磁滯控制(driver delay hysteresis control, DDHC)。 論文當中分析了此種驅動延遲磁滯控制D類音頻放大器(DDHC CDA)的總諧波失真(total harmonic distortion, THD)及電源雜訊抑制比(power-supply rejection ratio, PSRR)。分析的結果顯示，傳統的磁滯控制D類音頻放大器中所擁有的失真及雜訊來源在此DDHC CDA當中完全被消除了。並且此DDHC CDA去除了傳統上PWM(pulse width modualation)調變的閉迴路D類音頻放大器(PWM CDA)所具有的高頻失真來源。量測及分析的結果均顯示，此DDHC CDA相較於PWM CDA在整個音頻範圍內具有較佳的THD。 所提出的DDHC CDA使用了3.3V 0.35μm 2P4M CMOS製程實作，主要電路區域面積為0.53x0.4 mm^2。量測的THD+N在20Hz到20kHz之間均低於0.03%。當電源雜訊為-30dBV，217Hz的標準GSM雜訊時，PSRR為64dB。量測得到的SNR(signal-to-noise ratio)為80dB。當最大輸出功率時，電路的輸出功率效率是80%。

A simple circuit implementation of hysteresis controlled class D amplifier(CDA) is proposed in the thesis. Since the proposed circuit puts additional delay before the gate driver and switching stage in CDA to realize the hysteresis control, new control method is called driver delay hysteresiscontrol(DDHC). In this thesis, we analyse the total harmonic distortion(THD) and power supply rejection ratio(PSRR) of the proposed DDHC CDA. The analytical expression shows that the distortion source in the common hysteresis control(bang-bang control) CDA is completely dismissed in the DDHC CDA. The measurement results show that the proposed DDHC CDA has lower THD compared to PWM CDA in whole audio band. The proposed DDHC CDA is integrated and fabricated in 3.3V 0.35μm 2P4M CMOS process with 0.53x0.4 mm^2 active layout area. The measurement results show the THD+N ratio is flat and below 0.03% between 20Hz and 20kHz and PSRR is 64dB for a -30dBV,217Hz standard GSM perturbation noise. The measured SNR is 80dB at -60dB from full scale. The power efficiency is 80% at full power.